Intel Pentium M Processor Design Manual page 10

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Intel Pentium M Processor and Intel
Contents
Figures
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1 Intel Pentium
Configuration Example ............................................................................................................... 30
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2 Intel Pentium
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3 Intel E7501 Chipset MCH Quadrant Layout (Top View)........................................................... 33
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4 Intel ICH3-S Quadrant Layout (Top View)................................................................................ 34
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5 Intel P64H2 Quadrant Layout (Top View)................................................................................. 35
Ten Layer Stack-up, 50 Ω Board with 5-Mil Traces.................................................................... 37
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7 System Clocking Diagram Example ........................................................................................... 41
8 Shunt Source Termination .......................................................................................................... 42
9 Clock Skew As Measured from Agent to Agent.......................................................................... 44
10 Trace Spacing for HOST_CLK Clocks ....................................................................................... 45
11 Stuffing Options for CK408 and CK408B ................................................................................... 46
12 Topology for CLK66.................................................................................................................... 47
13 Clock Skew Requirements ......................................................................................................... 48
14 Example of Adding a Single Connector ...................................................................................... 49
15 Example of Adding Two Connectors and/or a Riser................................................................... 49
16 Topology for CLK33_ICH3-S ...................................................................................................... 50
17 Topology for CLK33 to PCI Device Down .................................................................................. 50
18 Topology for CLK33 to PCI Slot ................................................................................................. 51
19 Topology for CLK14.................................................................................................................... 52
20 Topology for USB_CLK .............................................................................................................. 53
21 Decoupling Capacitors Placement and Connectivity ................................................................. 54
22 Processor System Bus Topology ............................................................................................... 58
23 Trace Spacing vs. Trace-Reference Plane Example.................................................................. 59
24 Trace Spacing vs. Trace Width Example ................................................................................... 60
25 Processor RESET# Signal Routing Topology With NO ITP700FLEX Connector ...................... 60
26 Processor RESET# Signal Routing Topology With ITP700FLEX Connector ............................. 61
27 Routing Illustration for Topology 1A ........................................................................................... 66
28 Routing Illustration for Topology 1B ........................................................................................... 66
29 Routing Illustration for Topology 1C ........................................................................................... 67
30 Routing Illustration for Topology 2A ........................................................................................... 68
31 Routing Illustration for Topology 3 .............................................................................................. 69
32 Voltage Translation Circuit ......................................................................................................... 70
33 Resistor Divider Circuit For The MCH's HXSWNG And HYSWNG ............................................ 71
34 Trace Width and Spacing for All DDR Signals Except CMDCLK_x[3:0]/CMDCLK_x[3:0]# ....... 75
35 DIMM Connector Styles Supported ............................................................................................ 76
36 1-DIMM per Channel Implementation......................................................................................... 77
37 2-DIMMs per Channel Implementation ....................................................................................... 77
38 Example of Proper Single and Dual Rank Mixing....................................................................... 78
39 Example of Incorrect Single and Dual Rank Mixing ................................................................... 78
40 Dual Channel Source Synchronous Topology DIMM Solution ................................................... 81
41 Trace Length Matching Requirements for Source Synchronous Routing .................................. 81
42 Dual Channel 2-DIMM Command Clock Topology..................................................................... 83
43 Dual Channel Source Clocked Signal Topology......................................................................... 84
44 Dual Channel Chip Select Topology........................................................................................... 85
45 Dual Channel CKE Topology...................................................................................................... 86
46 Dual Channel Receive Enable Signal Routing Guidelines ......................................................... 87
47 Dual Channel DDRCOMP Resistive Compensation .................................................................. 88
48 DDR VREF Voltage Regulator ................................................................................................... 88
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E7501 Chipset Platform
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M Processor and Intel
M Processor Quadrant Layout (Top View) ....................................................... 32
E7501Chipset-Based System
Design Guide