Intel Pentium M Processor Design Manual page 8

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Intel Pentium M Processor and Intel
Contents
11.3 Processor Power Delivery Design Guidelines .................................................................. 192
11.3.1 Processor PLL Power Delivery ............................................................................ 192
11.3.2 Voltage Identification for Intel
11.3.3 V
CC_CORE
11.3.4 VCCP Output Requirements................................................................................ 194
11.3.5 Thermal Power Dissipation.................................................................................. 195
11.3.6 Voltage Regulator Topology ................................................................................ 196
11.3.7 Voltage Regulator Design Recommendations..................................................... 197
11.3.7.1 High Current Path, Top MOSFET Turned ON ..................................... 197
11.3.7.2 High Current Paths During Abrupt Load Current Changes.................. 198
11.3.7.3 High Current Paths During Switching Dead Time................................ 198
11.3.7.4 High Current Path With Bottom MOSFET(s) Turned ON..................... 199
11.3.7.5 General Layout Recommendations ..................................................... 199
11.3.8 Processor Decoupling Recommendations........................................................... 201
11.3.8.1 Transient Response............................................................................. 201
11.3.8.2 High/Mid Frequency and Bulk Decoupling........................................... 201
11.3.8.3 Processor Core Voltage Plane and Decoupling................................... 201
11.3.8.4 Processor Side Bus Voltage Plane Decoupling ................................... 202
11.3.8.5 GTLREF Layout and Routing Recommendations................................ 202
11.4 MCH Power Delivery Guidelines ...................................................................................... 203
11.4.1 DDR_VTT (1.25 V) Decoupling ........................................................................... 203
11.4.2 CPU_VCC (1.05 V Power Plane) ........................................................................ 203
11.4.3 DDR (2.5 V Power Plane).................................................................................... 204
11.4.4 Hub Interface (1.2 V Power Plane) ...................................................................... 205
11.4.5 Intel
11.4.6 MCH Power Sequencing Requirement................................................................ 206
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11.5 Intel ICH3-S Power Delivery Guidelines ......................................................................... 207
11.5.1 1.8 V/3.3 V Power Sequencing............................................................................ 207
11.5.2 3.3V / V5REF Sequencing................................................................................... 209
11.5.3 Intel
11.5.4 Intel
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11.6 Intel P64H2 Power Requirements .................................................................................. 212
11.6.1 Intel
11.6.2 Intel
11.6.3 PCIRST# Implementation .................................................................................... 213
11.6.4 Intel
12 High-Speed Design Concerns.................................................................................................. 215
12.1 Return Path....................................................................................................................... 215
12.2 Decoupling Theory............................................................................................................ 215
12.2.1 Bulk Decoupling................................................................................................... 216
12.2.2 High-Frequency Decoupling ................................................................................ 216
12.3 Serpentine Routing ........................................................................................................... 217
12.4 EMI Design Considerations .............................................................................................. 218
12.4.1 Brief EMI Theory.................................................................................................. 218
12.4.2 EMI Regulations and Certifications...................................................................... 218
12.5 EMI Design Considerations .............................................................................................. 219
12.5.1 Spread Spectrum Clocking (SSC) ....................................................................... 219
12.5.2 Differential Clocking............................................................................................. 220
12.5.3 PCI Bus Clock Control ......................................................................................... 221
12.5.4 EMI Test Capabilities........................................................................................... 221
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E7501 Chipset Platform
Power Sequencing ............................................................................. 194
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E7501 Chipset Filter Specifications (1.2 V Power Plane) .......................... 205
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ICH3-S Power Rails ................................................................................... 210
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ICH3-S Decoupling Recommendations ..................................................... 210
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P64H2 Current Requirements ................................................................... 212
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P64H2 Decoupling Requirements ............................................................. 212
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P64H2 Power Sequencing Requirement ................................................... 213
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Pentium M Processor....................................... 192
Design Guide