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Intel SL3QA - Pentium III 550 MHz Processor Specification

Intel SL3QA - Pentium III 550 MHz Processor Specification

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Intel
Pentium

III Processor

Specification Update
August 2008
Revision 060
244453-060
Document Number:

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Summary of Contents for Intel SL3QA - Pentium III 550 MHz Processor

  • Page 1: Iii Processor

    ® ® Intel Pentium III Processor Specification Update August 2008 Revision 060 244453-060 Document Number:...
  • Page 2 The Intel® Pentium® III processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

  • Page 3: Table Of Contents

    Contents Preface..........................8 Summary Tables of Changes....................10 Identification Information ....................20 Errata ..........................39 Specification Changes....................... 88 Specification Clarifications ....................89 Documentation Changes ....................93 Specification Update...

  • Page 4: Revision History

    Revision History Revision Description Date -001 This is the first Specification Update for Pentium® III processors. March 1999 -002 Added Erratum E42. Deleted Erratum E16 and renumbered existing April 1999 items. Corrected Errata table “Plans” column for E39. Updated the Pentium III Processor Identification Information table.
  • Page 5 Revision Description Date -011 Corrected an error in the Summary of Errata table. Erratum E56 was December 1999 incorrectly shown as applying to the Ca2 stepping. Erratum E56 does NOT apply to the Ca2 stepping. -012 Updated Preface to include new Pentium III processor datasheets. January 2000 Added 800-MHz Pentium III processor information to the DP Platform Population Matrix tables and the Pentium®...
  • Page 6 Revision Description Date -024 Updated Specification Update product key to include the Intel® December 2000 Pentium® 4 processor, Revised Erratum E2. Added new Documentation Changes E11 – E16. -025 Revised Erratum E2. Added new Documentation Changes E17 and E18. January 2001 Updated Processor Identification Table.
  • Page 7 Revision Description Date -044 Added new Doc Changes E3-E24. Removed parts with S-Spec numbers September 2002 SL6C2, SL6C3, SL6C4 and SL6BZ with Core Stepping tB1 from the Processor ID Information Table. -045 Added Doc Changes E25 to E32. Updated Summary of Changes. October 2002 -046 Updated DP FC-PGA2 Matrix table.

  • Page 8: Preface

    245264 datasheet Related Documents Document Title Document Number/Location Intel Architecture Software Developer’s Manual, Volumes 1, 2a, 2b, 3a 253665, 253666, and 3b 253667, 253668, 253669 Nomenclature Errata are design defects or errors. Errata may cause the Pentium III behavior to deviate from published specifications.
  • Page 9 Preface Documentation Changes include typos, errors, or omissions from the current published specifications. These changes will be incorporated in the next release of the specifications. Note: Errata remain in the specification update throughout the product’s lifecycle, or until a particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request.

  • Page 10: Summary Tables Of Changes

    The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
  • Page 11 Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology on 90-nm process technology Intel® Pentium® 4 processor on 90 nm process 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) Mobile Intel® Pentium® 4 processor-M 64-bit Intel®...
  • Page 12 Quad-Core Intel® Xeon® processor 5400 series Dual-Core Intel® Xeon® processor 5200 series AZ = Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45- nm Process AAA = Quad-Core Intel® Xeon® processor 3300 series AAB = Dual-Core Intel® Xeon® E3110 Processor AAC = Intel®...
  • Page 13 Summary Tables of Changes Plans ERRATA Differences exist in debug exception NoFix reporting FLUSH# servicing delayed while waiting for NoFix STARTUP_IPI in 2-way MP systems Code fetch matching disabled debug register NoFix may cause debug exception Double ECC error on read may result in NoFix BINIT# FP inexact-result exception flag may not be...
  • Page 14 Summary Tables of Changes Plans ERRATA MC2_STATUS MSR has model-specific error NoFix code and machine check architecture error code reversed Mixed cacheability of lock variables is NoFix problematic in MP systems MOV with debug register causes debug NoFix exception Upper four PAT entries not usable with Mode NoFix B or Mode C paging Data breakpoint exception in a displacement...
  • Page 15 Summary Tables of Changes Plans ERRATA Performance counters include Streaming Fixed SIMD Extensions L1 prefetch Fixed Snoop request may cause DBSY# hang Lower bits of SMRAM SMBASE register NoFix cannot be written with an ITP Task Switch May Cause Wrong PTE and PDE Fixed Access Bit to be Set Unsynchronized Cross-Modifying code...
  • Page 16 Summary Tables of Changes Plans ERRATA Fixed Livelock may occur due to IFU line eviction Selector for the LTR/LLDT register may get Fixed corrupted NoFix INIT does not clear global entries in the TLB NoFix VM bit will be cleared on a double fault handler NoFix Memory aliasing with inconsistent A and D...
  • Page 17 Summary Tables of Changes Plans ERRATA NoFix The FXSAVE, STOS, MOVS Instructions May Cause a Store Ordering Violation When Data Crosses a Page with a UC Memory Type POPF and POPFD Instructions that Set the NoFix Trap Flag Bit May Cause Unpredictable Processor Behavior Code Segment Limit Violation May Occur on NoFix...
  • Page 18 Summary Tables of Changes Plans ERRATA Using 2M/4M Pages When A20M# Is NoFix Asserted May Result in Incorrect Address Translations Values for LBR/BTS/BTM will be Incorrect E100 NoFix after an Exit from SMM E101 NoFix INIT Does Not Clear Global Entries in the TLB REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with E102...
  • Page 19 Summary Tables of Changes Number DOCUMENTATION CHANGES There are no Documentation Chnages in this revision of the Specification Update § Specification Update...

  • Page 20: Identification Information

    EDX register after the CPUID instruction is executed with a 2 in the EAX register. Other Intel microprocessor models or families may move this information to other bit positions or otherwise reformat the result returned by this instruction; generic code should parse the resulting token stream according to the definition of the CPUID instruction.
  • Page 21 While there are no known issues associated with the mixing of processors with differing cache sizes in a dual processor system, and Intel has done nothing to specifically prevent such system configurations from operating, Intel does not support such configurations since there may be uncharacterized errata that exist.
  • Page 22 Identification Information DP Platform Population Matrix for the Pentium ® III Processor with 100-MHz System Bus in the SECC and SECC2 Packages Pentium ® III 600E 550E 600E 600E Processor Stepping 450-MHz kB0 500-MHz kB0 450-MHz kC0 500-MHz kC0 550-MHz kC0 600-MHz kC0 600E-MHz cA2 650-MHz cA2...
  • Page 23 Identification Information DP Platform Population Matrix for the Pentium ® III Processor with 133-MHz System Bus in the SECC and SECC2 Package from 533MHz to 733MHz Pentium ® III 533E 600E 533E 600E 600E 533B 533B 600B B MHz B MHz B MHz B MHz B MHz...
  • Page 24 Identification Information DP Platform Population Matrix for the Pentium ® III Processor with 100- MHz System Bus in the FC-PGA370 Package from 500 MHz to 650 MHz ® Pentium 500E MHz 550E MHz 600E MHz 650 MHz 600E MHz 650 MHz 600E MHz Processor Stepping...
  • Page 25 Identification Information DP Platform Population Matrix for the Pentium ® III Processor with 133- MHz System Bus in the FC-PGA370 Package from 533 MHz to 800 MHz ® Pentium 533EB 600E 800E 600E 800E 800EB Processor Stepping 533EB-MHz cB0 600EB-MHz cB0 667-MHz cB0 733-MHz cB0 800EB-MHz cB0...
  • Page 26 Identification Information DP Platform Population Matrix for the Pentium ® III Processor with 133-MHz System Bus in the FC-PGA2 Package from 866 MHz to 1.4 GHz and uFCBGA2 Package for 800 MHz to 933 MHz ® Pentium 1.13 1.13 1.13 1.26 1.26 Processor...
  • Page 27 Identification Information Pentium® III Processor Identification and Package Information Speed ECC/ Processor Package Core (MHz) L2 Size RAM/ Non- Substrate S-Spec Stepping CPUID Core/Bus (Kbytes) Stepping Revision Revision Notes † SL364 0672h 450/100 T6P-e/A0 SECC2 1, 2, 4 SL365 0672h 500/100 T6P-e/A0 SECC2†...
  • Page 28 Identification Information Pentium® III Processor Identification and Package Information Speed ECC/ Processor Package Core (MHz) L2 Size RAM/ Non- Substrate S-Spec Stepping CPUID Core/Bus (Kbytes) Stepping Revision Revision Notes SL3VG 0681h 600EB/133 FC-PGA 9, 10 (370 pin) SL3VB 0681h 600EB/133 FC-PGA 7, 9, 10 (370 pin)
  • Page 29 Identification Information Pentium® III Processor Identification and Package Information Speed ECC/ Processor Package Core (MHz) L2 Size RAM/ Non- Substrate S-Spec Stepping CPUID Core/Bus (Kbytes) Stepping Revision Revision Notes SL45S 0683h 533EB/133 FC-PGA 10, 7 (370 pin) SL44G 0683h 550E/100 FC-PGA (370 pin) SL45T...
  • Page 30 Identification Information Pentium® III Processor Identification and Package Information Speed ECC/ Processor Package Core (MHz) L2 Size RAM/ Non- Substrate S-Spec Stepping CPUID Core/Bus (Kbytes) Stepping Revision Revision Notes SL463 0683h 800/100 FC-PGA 7, 10 (370 pin) SL43H 0683h 850/100 FC-PGA (370 pin) SL49G...
  • Page 31 Identification Information Pentium® III Processor Identification and Package Information Speed ECC/ Processor Package Core (MHz) L2 Size RAM/ Non- Substrate S-Spec Stepping CPUID Core/Bus (Kbytes) Stepping Revision Revision Notes SL4CC 0686h 850/100 FC-PGA (370 pin) SL4MC 0686h 850/100 FC-PGA 7, 13 (370 pin) SL4CB 0686h...
  • Page 32 Identification Information Pentium® III Processor Identification and Package Information Speed ECC/ Processor Package Core (MHz) L2 Size RAM/ Non- Substrate S-Spec Stepping CPUID Core/Bus (Kbytes) Stepping Revision Revision Notes SL4ZJ 068Ah 866/133 FC-PGA (370 pin) SL49H 068Ah 866/133 FC-PGA 7, 17 (370 pin) SL5B5/ 068Ah...
  • Page 33 Identification Information Pentium® III Processor Identification and Package Information Speed ECC/ Processor Package Core (MHz) L2 Size RAM/ Non- Substrate S-Spec Stepping CPUID Core/Bus (Kbytes) Stepping Revision Revision Notes SL4YV 068Ah 1.13 FC-PGA GHz/133 xxxiii(370 pin) SL5QK 068Ah 1.13GHz/13 FC-PGA2 18, 19,20 (370 pin) SL5GN...
  • Page 34 Identification Information Pentium® III Processor Identification and Package Information Speed ECC/ Processor Package Core (MHz) L2 Size RAM/ Non- Substrate S-Spec Stepping CPUID Core/Bus (Kbytes) Stepping Revision Revision Notes SL3H7 0681h 600EB/133 SECC2 10,20 SL3NB 0681h 600EB/133 SECC2 8,10,7,20 SL3KV 0681h 650/100 SECC2...
  • Page 35 Identification Information Pentium® III Processor Identification and Package Information Speed ECC/ Processor Package Core (MHz) L2 Size RAM/ Non- Substrate S-Spec Stepping CPUID Core/Bus (Kbytes) Stepping Revision Revision Notes SL3XJ 0683h 600EB/133 SECC2 8, 10 SL44Z 0683h 600EB/133 SECC2 8, 10 SL3XK 0683h 650/100...
  • Page 36 Identification Information Pentium® III Processor Identification and Package Information Speed ECC/ Processor Package Core (MHz) L2 Size RAM/ Non- Substrate S-Spec Stepping CPUID Core/Bus (Kbytes) Stepping Revision Revision Notes SL4KD 0686h 733/133 SECC2 8, 10 SL4FQ 0686h 733/133 SECC2 8, 10 SL4BZ 0686h 750/100...
  • Page 37 Identification Information The “E” and “B” designators distinguish between Pentium® III processors with the same core frequency different system frequencies and/or cache implementations. The “E” and “B” designators distinguish between Pentium® III processors with the same core frequency different system frequencies and/or cache...
  • Page 38 GRP1LN2: {Speed}/{Cache}/{Bus}/{Voltage} GRP2LN1: {FPO}-{S/N} GRP2LN2: PENTIUM III {S-Spec} FC-PGA2 370 Pin Package GRP1LN1 GRP1LN2 GRP1LN1: INTEL (m)(c) '01_-_{Country of Origin} GRP1LN2: {Core freq}/{Cache}/{Bus Freq}/{Voltage} GRP2LN1: {FPO}-{S/N} GRP2LN2: PENTIUM III {S-Spec} or PENTIUM III-S {S-Spec} GRP2LN1 GRP2LN2 Note: S above applies to 06BxH 512KB cache processor §...

  • Page 39: Errata

    The operating system uses the value contained in the FP Data Operand Pointer. Wrapping an 80 bit floating-point load around a segment boundary in this way is not a normal programming practice. Intel has not currently identified any software which exhibits this behavior.
  • Page 40 Case 6: Unlike previous versions of Intel Architecture processors, P6 family processors will not set the Bi bits for a matching disabled breakpoint unless at least one other breakpoint is enabled.
  • Page 41 FLUSH# assertion at this point. The FLUSH# will be serviced as soon as the processor is awakened by a STARTUP_IPI, before any other instructions are executed. Intel has not encountered any operating systems that are affected by this erratum.
  • Page 42 Errata Problem: For this erratum to occur, the following conditions must be met: • Machine Check Exceptions (MCEs) must be enabled. • A dataless transaction (such as a write invalidate) must be occurring simultaneously with a transaction which returns data (a normal read). •...
  • Page 43 Errata Note that even if this combination of instructions is encountered, there is also a dependency on the internal pipelining and execution state of both instructions in the processor. Implication: Inexact-result exceptions are commonly masked or ignored by applications, as it happens frequently, and produces a rounded result acceptable to most applications.
  • Page 44 Errata Workaround: If a system implementation must support both SMM and MCEs, the first thing the SMM handler code (when an I/O restart is to be performed) should do is check for a pending MCE. If there is an MCE pending, the SMM handler should immediately exit via an RSM instruction and allow the machine check exception handler to execute.
  • Page 45 Errata Workaround: None identified. Status: For the steppings affected see the Summary of Changes at the beginning of this section. E12. Machine Check Exception Handler Always Execute Successfully Problem: An asynchronous machine check exception (MCE), such as a BINIT# event, which occurs during an access that splits a 4 Kbyte page boundary, may leave some internal registers in an indeterminate state.
  • Page 46 Implication: Although BTMs may not be entirely reliable due to this erratum, the conditions necessary for this boundary condition to occur have only been exhibited during focused simulation testing. Intel has currently not observed this erratum in a system level validation environment.
  • Page 47 Results are unpredictable, depending on the particular application, and can range from no effect to the unexpected termination of the application due to an exception. Intel has observed this erratum only in a focused testing environment. Intel has not observed any commercially available operating system, application, or compiler that makes use of or generates this instruction.
  • Page 48 Errata Problem: The Memory Type field for nonmemory transactions such as I/O and Special Cycles are undefined. Although the Memory Type attribute for nonmemory operations logically should (and usually does) manifest itself as UC, this feature is not designed into the implementation and is therefore inconsistent. Implication: Bus agents may decode a non-UC memory type for nonmemory bus transactions.
  • Page 49 Workaround: Software should follow the recommendation in Section 8.2 of the Intel Architecture Software Developer’s Manual, Volume 3: System Programming Guide (Order Number 243192). This recommendation states that if the FPU will be used, software-initialization code should execute an FINIT/FNINIT instruction following a hardware reset.
  • Page 50 Errata Specifically, the sign may be incorrectly extended into bits 16-31 of the MMX technology register. Only the MMX technology register is affected by this erratum. The erratum only occurs when the three following steps occur in the order shown. The erratum may occur with up to 40 intervening instructions that do not modify the sign-extended value between steps 2 and 3.
  • Page 51 Errata Implication: The effect of incorrect execution will vary from unnoticeable, due to the code sequence discarding the incorrect bits, to an application failure. If the MMX technology-enabled application in which MOVD is used to manipulate pixels, it is possible for one or more pixels to exhibit the wrong color or position momentarily. It is also possible for a computational application that uses the MOVD instruction in the manner described above to produce incorrect data.
  • Page 52 MC2_STATUS MSR Has Model-Specific Error Code and Machine Check Architecture Error Code Reversed Problem: The Intel Architecture Software Developer’s Manual, Volume 3: System Programming Guide, documents that for the MCi_STATUS MSR, bits 15:0 contain the MCA (machine-check architecture) error code field, and bits 31:16 contain the model- specific error code field.
  • Page 53 (if the conditions above are satisfied). Intel has only encountered this problem in focus testing with artificially generated external events. Intel has not currently identified any commercial software which exhibits this problem.
  • Page 54 Errata Problem: The Page Attribute Table (PAT) contains eight entries, which must all be initialized and considered when setting up memory types for the Pentium III processor. However, in Mode B or Mode C paging, the upper four entries do not function correctly for 4-Kbyte pages.
  • Page 55 Errata Status: For the steppings affected see the Summary of Changes at the beginning of this section E30. SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null Segment Selector” to SS and CS Registers Problem: According to the processor specification, attempting to load a null segment selector into the CS and SS segment registers should generate a General Protection Fault (#GP).
  • Page 56 Implication: If an OS is used which can clear the D-bit for system pages, and which jumps to a new TSS on a task switch, then a condition may occur which results in a system hang. Intel has not identified any commercial software which may encounter this condition; this erratum was discovered in a focused testing environment.
  • Page 57 Errata E35. Transmission Error on Cache Read Problem: During reads of the L2 cache, the processor may use certain L2 cache optimizations that may result in a data transmission error Implication: Data corruption caused by this erratum will result in unpredictable system behavior. Workaround: It is possible for BIOS code to contain a workaround for this erratum.
  • Page 58 MMX™ register state. Implication: If this erratum occurs the floating-point exception will not be handled as expected. Workaround: Applications that follow Intel programming guidelines (empty all x87 registers before executing MMX technology instructions) will not be affected by this erratum Status:...
  • Page 59 Errata The P6 architecture allows for instructions (1) and (7) in P0 to be dispatched to the L1 cache simultaneously. If the two instructions are accessing the same memory bank in the L1 cache, the load (7) will be given higher priority and will complete, blocking instruction (1).
  • Page 60 Errata Problem: If a processor is underclocked at a core frequency to system bus frequency ratio of 2:1 and system bus ECC is enabled, the system bus ECC detection and correction will negatively affect internal timing dependencies. Implication: If system bus ECC is enabled, and the processor is underclocked at a 2:1 ratio, the system may behave unpredictably due to these timing dependencies.
  • Page 61 Prefetch Problem: The processor allows the measurement of the frequency and duration of numerous different internal and bus related events (see Intel Architecture Software Developer's Manual, Volume 3, for more details). The Streaming SIMD Extension (SSE) architecture provides a mechanism to pre-load data into the L1 cache, bypassing the L2 cache.
  • Page 62 Errata Implication: This erratum may occur on a system with any number of processors. However, the probability of occurrence increases with the number of processors. If this erratum does occur, the system will hang with DBSY# asserted. At this point, the system requires a hard reset.
  • Page 63 Implication: In this case, the phrase "unexpected execution behavior" encompasses the generation of most of the exceptions listed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide, including a General Protection Fault (GPF). In the event of a GPF the application executing the unsynchronized XMC operation would be terminated by the operating system.
  • Page 64 Errata 2. Externally condition the SMI# signal prior to providing it to the processor's SMI# pin. These workarounds should be evaluated on a design-by-design basis. Status: For the steppings affected see the Summary of Changes at the beginning of this section E52.
  • Page 65 Illegal-Instruction/Page-Miss Combination Problem: Intel's 32-bit Instruction Set Architecture (ISA) utilizes most of the available op-code space; however some byte combinations remain undefined and are considered illegal instructions. Intel processors detect the attempted execution of illegal instructions and signal an exception.
  • Page 66 These combinations are not normally generated in the course of software programming, nor are such sequences known by Intel to be generated in commercially available software and tools. Development tools (compilers, assemblers) do not generate this type of code sequence, and will normally flag such a sequence as an error.
  • Page 67 Errata 3. The register is then copied to an MMX™ technology register using the MOVD, or converted to single precision floating-point and moved to an MMX technology register using the CVTSI2SS instruction prior to any other operations on the sign- extended value, or inserted into an MMX™...
  • Page 68 Errata replaced with any 8-bit or 16-bit general-purpose register. The CBW and IMUL (opcode F6 /5) instructions are specific to the EAX register only. In the above example, EAX is forced to contain 0 by the XOR or SUB instructions. Since the four types of the MOVSX or IMUL instructions and the CBW instruction only modify bits 15:8 of EAX by sign extending the lower 8 bits of EAX, bits 31:16 of EAX should always contain 0.
  • Page 69 Errata MOVSX AX, BL (or other MOVSX, other IMUL or CBW instruction) *MOV EAX, EAX MOVD MM0, EAX or CVTSI2SS MM0, EAX 3. Avoid using a sub or xor to zero a partial register prior to the use of any of these three instructions.
  • Page 70 Errata SC242-based platform designs in which VTT leads the processor input voltage may reduce the occurrence of the erratum by connecting SC242 pin B20 (RESERVED) to pin B9 (VTT). PGA370-based platform designs in which VTT leads the processor input voltage can reduce the occurrence of the erratum by connecting pin G37 (RESERVED) to motherboard VTT or short the PGA370 socket pin G37 to AH20 or G35 (both VTT).
  • Page 71 Errata E64. Cache Line Reads May Result in Eviction of Invalid Data Problem: A small window of time exists in which internal timing conditions in the processor cache logic may result in the eviction of an L2 cache line marked in the invalid state. Implication: There are three possible implications of this erratum: 1.
  • Page 72 Errata Implication: If this erratum occurs, the processor will hang in a live lock-situation, and the system will require a reset to continue normal operation. Workaround: None identified Status: For the steppings affected see the Summary of Changes at the beginning of this section.
  • Page 73 Workaround: Although it is possible to have a single physical page mapped by two different linear addresses with different memory types, Intel has strongly discouraged this practice as it may lead to undefined results. Software that needs to implement memory aliasing should manage the memory type consistency...
  • Page 74 The system may hang if machine check exceptions are disabled. Intel has not observed the occurrence of this erratum while running commercially available applications or operating systems. Workaround: Software can avoid this erratum by placing a serializing instruction between code fetches between different memory types.
  • Page 75 Errata Workaround: Software should always poll the Delivery Status bit in the APIC ICR and ensure that it is '0' (Idle) before writing a new value to the ICR. Status: For the steppings affected see the Summary of Changes at the beginning of this section E76.
  • Page 76 Errata Workaround: To prevent the risk of power-on boot failures or catastrophic thermal failures, a platform workaround is required. The system must provide a rising edge on the TCK signal during the power-on sequence that meets all of the following requirements: •...
  • Page 77 Errata • The example workaround circuit assumes that the PWRGD inputs into the processors are open collector. Tying the PWRGD inputs together in a Wired-AND fashion allows each processor to receive PWRGD at the same time but at the latter of the 2 separate PWRGD assertions. If separation of the PWRGD inputs to each processor is required, extra circuitry will be required.
  • Page 78 A lockable instruction with memory operand that spans across two pages may, given some rare internal conditions, hang the system. Implication: When this erratum occurs, the system may hang. Intel has not observed this erratum with any commercially available software or system.
  • Page 79 In the event that the WB to WC aliasing case occurs and incorrect data is written to memory, the end result would vary from benign to operating system or application failure. Intel has not observed either aspects of this erratum in commercially available software.
  • Page 80 0x0. Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software, or system.
  • Page 81 Errata Implication: When this erratum occurs, the memory page may be as UC (rather than WC). This may have a negative performance impact. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. E91. Under Certain Conditions LTR (Load Task Register) Instruction May Result in System Hang Problem: An LTR instruction may result in a system hang if all the following conditions are met:...
  • Page 82 Invalid entries in the Page-Directory-Pointer-Table Register (PDPTR) that have the reserved bits set to one may cause a General Protection (#GP) exception. Implication: Intel has not observed this erratum with any commercially available software. Workaround: Do not set the reserved bits to one when PDPTR entries are invalid.
  • Page 83 #GP fault (general protection exception). Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
  • Page 84 Problem: Under certain conditions as described in the Software Developers Manual section “Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to Specification Update...
  • Page 85 Implication: Data in the created stack frame may be altered following a fault on the ENTER instruction. Please refer to "Procedure Calls For Block-Structured Languages" in IA- 32 Intel® Architecture Software Developer’s Manual, Vol. 1, Basic Architecture, for information on the usage of the ENTER instructions. This erratum is not expected to occur in ring 3.
  • Page 86 Errata transferring to ring 0. Intel has not observed this erratum on any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes E105. Unaligned Accesses to Paging Structures May Cause the Processor to...
  • Page 87 Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of the erratum condition while the counter is active. Intel has not observed this erratum with any commercially available software.

  • Page 88: Specification Changes

    The Specification Changes listed in this section apply to the following documents: • Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.13 GHz datasheet • Intel® Pentium® III Processor for the PGA370 Socket up to 1.13 GHz datasheet •...

  • Page 89: Specification Clarifications

    The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M, Pentium 4, and Intel Xeon processors) is a 64-bit counter that is set to 0 following a RESET of the processor. Following a RESET, the counter will increment even when the...
  • Page 90 The RDMSR and WRMSR instructions read and write the time-stamp counter, treating the time-stamp counter as an ordinary MSR (address 10H). In the Pentium 4, Intel Xeon, and P6 family processors, all 64-bits of the time-stamp counter are read using RDMSR (just as with RDTSC).
  • Page 91 Specification Clarifications Counting Clocks The count of cycles, also known as clockticks, forms a the basis for measuring how long a program takes to execute. Clockticks are also used as part of efficiency ratios like cycles per instruction (CPI). Processor clocks may stop ticking under circumstances like the following: The processor is halted when there is nothing for the CPU to do.
  • Page 92 Specification Clarifications The time-stamp counter and the non-sleep clockticks count may not agree in all cases and for all processors. See Section 10.8 for more information on counter operation. § Specification Update...

  • Page 93: Documentation Changes

    All Documentation Changes will be incorporated into a future version of the appropriate Pentium III processor documentation. Note: Documentation changes for Intel® 64 and IA-32 Architectures Software Developer’s Manual volumes 1, 2a, 2b, 3a and 3b are posted in a separate document "Intel®...

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