Single Channel Source Clocked Signal Group Routing; Single Channel Source Clocked Signal Topology - Intel Pentium M Processor Design Manual

6.4.4

Single Channel Source Clocked Signal Group Routing

The MCH drives the command clock signals and the source-clocked signals together. That is, the
MCH drives the command clock in the center of the valid window, and the source-clocked signals
propagate with the command clock signal. Therefore, the critical timing is the difference between
the command clock flight time and the source clocked signal flight time. The absolute flight time is
not as critical.
When resistor packs are used for the termination resistors, it is suggested that source synchronous
signals not be mixed with Source Clocked, Chip Select, or Clock Enable signals within the same
resistor pack for validation purposes.
Table 45. Single Channel Source Clocked Signal Group Routing Guidelines
Signal Group
Topology
Reference Plane
Trace Impedance (Z
Nominal Trace Width
Nominal Trace Spacing
MCH to DIMM1 Trace Length
DIMM to DIMM Trace Length
DIMM to Rtt Trace Length
Termination Resistor (Rtt)
MCH Breakout Guidelines
NOTES:
1. No length tuning required.
2. Breakout distance is measured from outer ball array.
Figure 62.

Single Channel Source Clocked Signal Topology

NOTE: Indicated lengths measure from the MCH component die pad to the DIMM connector pin.
Design Guide
®
Intel Pentium
1-DIMM Solution
Parameter
0°, 25°, 90°
50 Ω ± 10%
)
0
15 mils
1.8" to 5.5"
Not Applicable
39.2 Ω ± 1%
5/5 (1:1),
2
< 500 mils
RAS#, CAS#, WE#
Channel A
MA[12:0], BA[1:0]
MCH
®
M Processor and Intel
Memory Interface Routing Guidelines
2-DIMM Solution
25°
RAS#, CAS#, WE#, MA[12:0], BA[1:0]
Daisy Chain
Ground
50 Ω ± 10%
5 mils 5 mils
15 mils
1.8" to 5.5"
1.8" to 2.2"
< 0.8" < 0.8"
39.2 Ω ± 1%
5/5 (1:1),
< 500 mils
MCH to DIMM1 DIMM to
DIMM
DIMMs
®
E7501 Chipset Platform
2-DIMM Solution
Reference
90°
Figure 62
Figure 59
50 Ω ± 10%
Table 42
5 mils Figure 59
15 mils Figure 34
1.8" to 5.5" Figure 62
1.0" to 1.2" Figure 62
< 0.8" Figure 62
39.2 Ω ± 1%
Figure 62
5/5 (1:1),
< 500 mils
DDR VTERM
(1.25V)
Rtt
Rtt
DIMM
to Rtt
101