Routing Illustration For Topology 1C; Layout Recommendations For Topology 1B; Layout Recommendations For Topology 1C - Intel Pentium M Processor Design Manual

Table 24.

Layout Recommendations for Topology 1B

L1
0.5" – 12.0"
5.1.7.1.3 Topology 1C: Open Drain (OD) Signals Driven
by the Intel
The Topology 1C OD signal PROCHOT#, should adhere to the following routing and layout
recommendations.
signal of the Intel Pentium M processor. The routing guidelines allows the signal to be routed as
either a micro-strip or strip-line using 50 Ω ± 10% characteristic trace impedance.
the recommended implementation for providing voltage translation between the Intel Pentium M
processor's PROCHOT# signal and the ICH3-S or any other system receiver that utilizes a 3.3 V
interface voltage (shown as V_IO_RCVR).
Series resistor R
resistor. R
to emphasize the placement of R
Q1 BJT is a specific implementation of the generalized voltage translator circuit shown in
Figure 32. R
pull-up voltage for termination resistor R
It is recommended that PROCHOT# be routed to voltage translation logic shown in
receiver at the output of the voltage translation circuit may be the ICH3-S or any optional system
receiver that may function properly with the PROCHOT# signal given the nature and usage model
of this pin. Intel recommends that the ICH3-S be used as the receiver, thus the translated
PROCHOT# signal should be routed to the THRM# signal of the ICH3-S. PROCHOT# is capable
of toggling hundreds of times per second to signal a hot temperature condition.
Figure 29.

Routing Illustration for Topology 1C

Table 25.

Layout Recommendations for Topology 1C

L1
0.5" – 12.0"
Design Guide
®
Intel Pentium
L2 L3
0" – 3.0" 0" – 3.0"
® ®
Pentium M Processor – PROCHOT#
Table 25 lists the recommended routing requirements for the PROCHOT#
is a component of the voltage translation logic and serves as a driver isolation
s
is shown separated by distance L3 from the first bipolar junction transistor (BJT), Q1,
s
with respect to Q1. The placement of R
s
should be placed at the beginning of the T-split from the PROCHOT# signal. The
s
CPU
VCCP
L1
Rtt
L2
Rs
L2 L3
0" – 3.0" 0" – 3.0"
®
M Processor and Intel
System Bus Routing Guidelines
R1
56 Ω ± 5% 56 Ω ± 5%
is V (1.05 V).
tt CCP
3.3V
R1
Q2
Q1
L3
3904
L4 R R1
S
330 Ω 1.3 k Ω
0.5" –
12.0" ± 5% ± 5%
®
E7501 Chipset Platform
R Transmission Line Type
tt
Micro-strip and Strip-line
Figure 29
a distance L3 before the
s
Figure
®
Intel
ICH3-S
3.3V
(or sys. receiver)
V_IO_RCVR
R2
L4
3904
Transmission
R2 R
tt
Line Type
330 Ω ± 56 Ω ±
Micro-strip and
5% 5% Strip-line
shows
29. The
67