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6.4.2
Single Channel Source Synchronous Signal Group Routing
The MCH source synchronous signals are divided into groups consisting of data bits (DQ) and
check bits (CB). An associated strobe (DQS) exists for each DQ and CB group, as shown in
Table
42. The MCH supports both x4 and x8 devices, and the number of signals in each data group
depends on the type of devices that are populated. For example, when x4 devices are populated, the
72-bit channel is divided into 18 data groups (16 groups consisting of four data bits each, and two
groups consisting of four check bits each). One DQS is associated with each of these groups
(18 total). Likewise, when x8 devices are populated, the 72-bit channel is divided into a total of
nine data groups. In this case, only nine of the 18 strobes are used.
Table 42.
Single Channel DQ/CB to DQS Mapping
† In x4 configurations, the high DQS is associated with the high nibble and the low
DQS is associated with the low nibble. In x8 configurations, only the low DQS is
used.
Table 43
group must be length matched to the associated DQSs, as described in
Tuning". Length matching past the last DIMM connector is not critical. Route all data signals and
their associated strobes on the same layer. Try to maintain routing the signals on the same layer.
When a layer transition must occur, minimize the discontinuity in the ground reference plane. The
source synchronous signals require series termination resistors (Rs) placed close to the first DIMM
connector, and parallel termination resistors (Rtt) placed after the last DIMM connector. These
solutions do not require DQS to CMDCLK pair length matching.
When resistor packs are used for the termination resistors, it is suggested that source synchronous
group signals not be mixed with Source Clocked, Chip Select, or Clock Enable signals within the
same resistor pack for validation purposes.
Design Guide
®
Intel
Pentium
Data Group
DQ_x[7:0]
DQ_x[15:8]
DQ_x[23:16]
DQ_x[31:24]
DQ_x[39:32]
DQ_x[47:40]
DQ_x[55:48]
DQ_x[63:56]
CB_x[7:0]
states the routing requirements for the DQ, DQS and CB signals. All signals in a data
®
M Processor and Intel
Memory Interface Routing Guidelines
†
Associated Strobe
DQS0, DQS9
DQS1, DQS10
DQS2, DQS11
DQS3, DQS12
DQS4, DQS13
DQS5, DQS14
DQS6, DQS15
DQS7, DQS16
DQS8, DQS17
®
E7501 Chipset Platform
Section 12.6, "Length
97
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