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®
®
Intel
Pentium
M Processor and Intel
Platform Power Delivery Guidelines
11.2.1
Processor Core Voltage (V
®
The Intel
automatic selection of power supply voltages. The VID pins for the Intel Pentium M processor are
CMOS outputs driven by the processor VID circuitry. For more details about VR design to support
the Intel Pentium M processor power supply requirements .
11.2.2
System Bus Voltage (VCCP 1.05 V)
Most Intel Pentium M processor system bus signals use Assisted Gunning Transceiver Logic
(AGTL+) signalling technology. This signalling technology provides improved noise margins and
reduced ringing through low-voltage swings and controlled edge rates. The termination voltage
level for the Intel Pentium M processor AGTL+ signals is VCCP = 1.05 V (nominal).
The AGTL+ inputs require a reference voltage (GTLREF), which is used by the receivers to
determine when a signal is a logical 0 or a logical 1. GTLREF must be generated on the system
board. Termination resistors are provided on the processor silicon and are terminated to its I/O
voltage (VCCP).
The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
system bus, including trace lengths, is highly recommended when designing a system.
Note: VCCP on the Intel Pentium M processor corresponds to CPU_VCC on the Intel
11.2.3
2.5 V
The 2.5 V power plane is used to provide power to the DDR DRAM core, the MCH DDR I/O ring,
and reference voltage to the 1.25 V switching regulator. The 2.5 V power plane is created using a
switching regulator, which should be able to support up to 26 A of current. This switching regulator
receives its input directly from the 5 V power rail of the power supply. The DDR DRAM core
requires at most 20.0 A of current. This value is a worst-case current, and is based on DRAM
vendor specific specification for maximum current. Power levels may vary. In some cases, current
requirements may be less than half of this maximum value, but a maximum current level of 20.0 A
should be used to allow interoperability among DRAM devices. The current dedicated for VDD in
the MCH is 6.8 A. This regulator is required in all designs.
11.2.4
1.25 V
A voltage regulator derived off 2.5 V produces two 1.25 V rails. One is for the MCH reference
voltage (VREF); the other is for DDR termination voltage (V
divides the 2.5 V power rail by 2 to drive 1.25 V reference voltage. This provides some
common-mode noise rejection between the DDR termination and I/O voltages. The entire power
plane requires about 12 A of maximum current, and may be achieved by using either one or two
regulators (one for both channels or one for each channel).
190
®
E7501 Chipset Platform
®
Pentium
M processor uses six voltage identification pins, VID[5:0], to support
)
CC_CORE
). The switching regulator
TERM
®
E7501 MCH.
Design Guide
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