Combination Host-Side/Device-Side Cable Detection; Combination Host-Side/Device-Side Ide Cable Detection - Intel Pentium M Processor Design Manual

® ®
Intel Pentium M Processor and Intel
I/O Controller Hub 3 (Intel
To determine when Ultra DMA modes greater than two (Ultra ATA/33) may be enabled, the
ICH3-S requires the system software to attempt to determine the cable type used in the system.
When the system software detects an 80-conductor cable, it may use any Ultra DMA mode up to
the highest transfer mode supported by both the chipset and the IDE device. When a 40-conductor
cable is detected, the system software must not enable modes faster than Ultra DMA Mode 2
(Ultra ATA/33).
Intel recommends that cable detection be performed using a combination Host-Side/Device-Side
detection mechanism.
9.1.2.1

Combination Host-Side/Device-Side Cable Detection

Host-side detection (described in the ATA/ATAPI-4 Standard, Section 5.2.11) requires the use of
two GPI pins (one for each IDE channel). The proper way to connect the PDIAG#/CBLID# signal
of the IDE connector to the host is shown in
resistor to 5 V on this signal. Not all of the GPI and GPIO pins on the ICH3-S are 5 V tolerant. A
10 kΩ
± 5%
when a device is not present. The pull-down resistor also allows for the use of a non-5 V tolerant
GPIO.
Figure 106.

Combination Host-Side/Device-Side IDE Cable Detection

Intel
ICH3-S
Resistor required for
non 5V tolerant GPI
Intel
ICH3-S
Resistor required for
non 5V tolerant GPI
This mechanism allows the BIOS, after diagnostics, to sample PDIAG#/CBLID#. When the signal
is high, then a 40-conductor cable is present in the system and Ultra DMA modes greater than
Mode 2 (Ultra ATA/33) must not be enabled.
When PDIAG#/CBLID# is detected low, an 80-conductor cable may be in the system, or there may
be a 40-conductor cable and a legacy slave device (Device 1) that does not release the PDIAG#/
CBLID# signal as required by the ATA/ATAPI-4 standard. In this case, BIOS should check the
IDENTIFY DEVICE information in a connected device that supports Ultra DMA modes higher
154
®
E7501 Chipset Platform
®
ICH3-S)
pull-down resistor on PDIAG#/CBLID# is required to prevent the GPIO from floating
To secondary
IDE connector
40-conductor
GPIO
cable
®
PDIAG#/
CBLID#
GPIO
Ω
10 k
To secondary
IDE connector
80-conductor
GPIO
IDE cable
®
PDIAG#/
CBLID#
GPIO
Ω
10 k
Figure 106. All IDE devices have a 10 kΩ pull-up
IDE drive
5 V
Ω
10 k
PDIAG#
IDE drive
5 V
Ω
10 k
PDIAG#
Open
IDE drive
5 V
Ω
10 k
PDIAG#
IDE drive
5 V
Ω
10 k
PDIAG#
IDE_Combo_Cable_Det
Design Guide