Intel Pentium M Processor Design Manual page 4

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Intel Pentium M Processor and Intel
Contents
5.1.3 Recommended Stack-up Routing and Spacing Assumptions ............................... 59
5.1.4 Trace Space to Trace - Reference Plane Separation Ratio .................................. 59
5.1.4.1
5.1.4.2
5.1.5 Source Synchronous Signals................................................................................. 61
5.1.5.1
5.1.5.2
5.1.5.3
5.1.6 Common Clock Signals ......................................................................................... 64
5.1.7 Asynchronous Signals ........................................................................................... 65
5.1.7.1
5.1.7.2
5.1.8 AGTL+ I/O Buffer Compensation........................................................................... 70
5.1.8.1
5.1.8.2
5.1.9 Intel
5.1.10 Intel
Design Recommendations..................................................................................... 72
6 Memory Interface Routing Guidelines....................................................................................... 73
6.1 DDR Channel Impedance Requirements ........................................................................... 74
6.2 DIMM Types ....................................................................................................................... 75
6.3 Dual Channel DDR Overview ............................................................................................. 76
6.3.1 Dual Channel Source Synchronous Signal Group Routing ................................... 78
6.3.2 Dual Channel Command Clock Routing ................................................................ 82
6.3.3 Dual Channel Source Clocked Signal Group Routing ........................................... 83
6.3.4 Dual Channel Chip Select Routing ........................................................................ 84
6.3.5 Dual Channel Clock Enable Routing ..................................................................... 85
6.3.6 Dual Channel DC Biasing Signals ......................................................................... 86
6.3.6.1
6.3.6.2
6.3.6.3
6.3.6.4
6.3.7 Dual Channel DDR Signal Termination and Decoupling ....................................... 90
6.3.8 2.5 Volt Decoupling Requirements ........................................................................ 91
6.4 Single Channel DDR Overview........................................................................................... 94
6.4.1 Unused Channel Termination ................................................................................ 96
6.4.2 Single Channel Source Synchronous Signal Group Routing................................. 97
6.4.3 Single Channel Command Clock Routing ........................................................... 100
6.4.4 Single Channel Source Clocked Signal Group Routing....................................... 101
6.4.5 Single Channel Chip Select Routing.................................................................... 102
6.4.6 Single Channel Clock Enable Routing................................................................. 103
6.4.7 Single Channel DC Biasing Signals..................................................................... 104
6.4.7.1
6.4.7.2
6.4.7.3
6.4.7.4
6.4.8 Single Channel DDR Signal Termination and Decoupling................................... 108
6.4.9 2.5 V Decoupling Requirements .......................................................................... 109
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E7501 Chipset Platform
Trace Space to Trace Width Ratio......................................................... 59
Processor RESET# Signal..................................................................... 60
Source Synchronous General Routing Guidelines ................................ 61
Source Synchronous - Data .................................................................. 62
Source Synchronous - Address ............................................................ 63
Topologies ............................................................................................. 65
Voltage Translation Logic ...................................................................... 69
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Intel Pentium M Processor AGTL+ I/O Buffer Compensation ........... 70
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Intel E7501 Chipset AGTL+ I/O Buffer Compensation ........................ 70
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Pentium M Processor System Bus Strapping ............................................ 71
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Pentium M Processor VCCSENSE/VSSSENSE
Dual Channel Receive Enable Signal (RCVEN#) .................................. 87
Dual Channel DDRCOMP...................................................................... 87
Dual Channel DDRVREF and ODTCOMP ............................................ 88
Dual Channel DDRCVO......................................................................... 90
Single Channel Receive Enable Signal (RCVEN#) ............................. 104
Single Channel DDRCOMP ................................................................. 104
Single Channel DDRVREF and ODTCOMP........................................ 105
Single Channel DDRCVO .................................................................... 107
Design Guide