Intel Pentium M Processor Design Manual page 14

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Intel Pentium M Processor and Intel
Contents
Tables
1 Reference Documents ................................................................................................................ 19
2 Conventions and Terminology .................................................................................................... 21
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3 Intel Pentium
4 Board Requirements................................................................................................................... 38
5 CK408 Clock Groups .................................................................................................................. 39
6 Platform System Clock Reference.............................................................................................. 39
7 HOST_CLK[1:0]# Routing Guidelines ........................................................................................ 43
8 CLK66 Routing Guidelines ......................................................................................................... 47
9 CLK33_ICH3-S Routing Guidelines ........................................................................................... 50
10 CLK33 Routing Guidelines for PCI Device Down ....................................................................... 51
11 CLK33 Routing Guidelines for PCI Slot ...................................................................................... 51
12 CLK14 Routing Guidelines ......................................................................................................... 52
13 USBCLK Routing Guidelines ...................................................................................................... 53
14 System Bus Signal Groups......................................................................................................... 57
15 System Bus Routing Summary................................................................................................... 58
16 Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector ........................... 61
17 2X and 4X Signal Groups ........................................................................................................... 61
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18 Intel Pentium
Signal Trace Length Match Mapping .......................................................................................... 62
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19 Intel Pentium
Data Signal Routing Guidelines.................................................................................................. 63
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20 Intel Pentium
Signal Trace Length Mismatch Mapping .................................................................................... 63
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21 Intel Pentium
Address Signal Routing Guidelines ............................................................................................ 64
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22 Intel Pentium
Internal Layer Routing Guidelines .............................................................................................. 65
23 Layout Recommendations for Topology 1A ............................................................................... 66
24 Layout Recommendations for Topology 1B ............................................................................... 67
25 Layout Recommendations for Topology 1C ............................................................................... 67
26 Layout Recommendations for Topology 2A ............................................................................... 68
27 Layout Recommendations for Topology 2B ............................................................................... 68
28 Layout Recommendations for Topology 3 .................................................................................. 69
29 ITP Signal Default Strapping When ITP Debug Port Not Used .................................................. 71
30 DDR Channel Signal Groups...................................................................................................... 73
31 Trace Width to Impedance Requirements .................................................................................. 74
32 DQ/CB to DQS Mapping............................................................................................................. 78
33 Dual Channel Source Synchronous Signal Group Routing Guidelines ...................................... 80
34 Dual Channel Command Clock Pair Routing Guidelines ........................................................... 82
35 Dual Channel Source Clocked Signal Group Routing Guidelines .............................................. 83
36 Dual Channel Chip Select Routing Guidelines ........................................................................... 84
37 Dual Channel Clock Enable Routing Guidelines ........................................................................ 86
38 Receive Enable Routing Guidelines ........................................................................................... 87
39 DDRCOMP Routing Guidelines.................................................................................................. 87
40 DDRCVO Routing Guidelines..................................................................................................... 90
41 Channel B Signal Terminations .................................................................................................. 96
42 Single Channel DQ/CB to DQS Mapping ................................................................................... 97
43 Single Channel Source Synchronous Signal Group Routing Guidelines ................................... 98
44 Single Channel Command Clock Pair Routing Guidelines ....................................................... 100
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E7501 Chipset Platform
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M Processor or Intel E7501 Chipset Platform Peak Bandwidth Summary..... 29
M Processor System Bus Data Source Synchronous
M Processor System Bus Source Synchronous
M Processor System Bus Address Source Synchronous
M Processor System Bus Source Synchronous
M Processor System Bus Common Clock Signal
Design Guide