®
®
Intel
Pentium
M Processor and Intel
Memory Interface Routing Guidelines
Table 43.
Single Channel Source Synchronous Signal Group Routing Guidelines
Parameter
Signal Group
Topology
Reference Plane
MCH to Rs Trace
Impedance (Z
Rs to Rtt Trace
Impedance (Z
MCH to Rs Trace
Width
Rs to Rtt Trace
Width
Nominal Trace
Spacing
MCH to DIMM1
Trace Length
Rs to DIMM1 Trace
Length
DIMM to DIMM
Trace Length
DIMM to Rtt Trace
Length
Series Resistor (Rs)
Termination Resistor
(Rtt)
MCH Breakout
Guidelines
Length Tuning
Requirements
NOTES:
1. No Rs is required. Instead, change the impedance at the first DIMM pin.
2. The DQS pair in the group must also be tuned to each other with this parameter. The DQ and DQS lines in
the same group must be length tuned to all DIMMs. Tune all lengths to the Intel
trace lengths.
3. Route all data signals and their associated strobes on the same layer from MCH to Rtt.
4. The MCH to DIMM1 trace length is defined as Intel E7501 MCH die pad (PCB trace velocity equivalent,
see
Section 12.6, "Length
5. Within the same group, this length range should not vary by more than 50 mils. However, the length may
be anywhere from 1.0" to 1.2".
6. Ensure angled DIMM connector pin length differences are accounted for when tuning lengths.
7. Within the same group, this length range should not vary by more than 50 mils. However, the length may
be anywhere from 1.8" to 2.2".
8. Breakout distance is measured from outer ball array.
98
®
E7501 Chipset Platform
1-DIMM Solution
6
6
0°
, 25°
, 90°
3
50 Ω ± 10%
)
0
50 Ω ± 10%
)
0
5 mils
5 mils
15 mils ± 1 mil
1.8" to 5.5"
4
0.1" to 0.8"
Not Supported
< 0.8"
10 Ω ± 2%
39.2 Ω ± 1%
5/5 (1:1),
8
< 500 mils
DQ to DQS: ± 25 mil
Tuning") to DIMM1 pin.
2-DIMM Solution
6
25°
DQ[63:0], CB[7:0], DQS[17:0]
Daisy Chain
Ground
50 Ω ± 10%
50 Ω ± 10%
5 mils
5 mils
15 mils ± 1 mil
1-8" to 4.5"
0.1" to 0.8"
7
1.8" to 2.2" ± 50 mils
1.0" to 1.2"± 50 mils
< 0.8"
10 Ω ± 2%
39.2 Ω ± 1%
5/5 (1:1),
< 500 mils
2
2
DQ to DQS: ± 25 mil
DQ to DQS: ± 25 mil
2-DIMM Solution
Reference
90°
Figure 59
Figure 59
50 Ω ± 10%
Table 42
50 Ω ± 10%
Table 42
5 mils
Figure 59
5 mils
Figure 59
15 mils ± 1 mil
Figure 59
1-8" to 6.0"
Figure 59
0.1" to 0.8"
Figure 59
5
Figure 59
< 0.8"
Figure 59
10 Ω ± 2%
Figure 59
39.2 Ω ± 1%
Figure 59
5/5 (1:1),
< 500 mils
Figure
2
Section 12.6
®
E7501 MCH package
Design Guide
60,
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