Intel Pentium M Processor Design Manual page 7

9.7.1.1
9.7.1.2
9.7.2 General LAN Routing Guidelines and Considerations......................................... 170
9.7.2.1
9.7.2.2
9.7.2.3
9.7.2.4
9.7.2.5
9.7.2.6
9.7.2.7
9.7.3 Intel
9.7.3.1
9.7.3.2
9.7.3.3
9.7.4 Critical Dimensions .............................................................................................. 176
9.7.4.1
9.7.4.2
9.7.5 Terminating Unused Connections .......................................................................177
9.7.5.1
10 Debug Port and Logic Analyzer Interface ............................................................................... 179
10.1 ITP Support....................................................................................................................... 179
10.1.1 Overview .............................................................................................................. 179
10.1.2 Implementation .................................................................................................... 179
10.2 Recommended Onboard ITP700FLEX Implementation ................................................... 180
10.2.1 ITP Signal Routing Guidelines ............................................................................. 180
10.2.1.1 TDI, TMS and TRST# Routing Requirements ..................................... 180
10.2.1.2 TCK and TDO Routing Requirements ................................................. 181
10.2.1.3 BPMx# Routing Requirements............................................................. 181
10.2.1.4 RESET# Routing Guidelines................................................................182
10.2.1.5 BCLK Routing Requirements ............................................................... 182
10.2.1.6 ITPFLEX Routing Requirement Summary ...........................................182
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10.3 Intel Pentium
10.3.1 Overview .............................................................................................................. 184
10.3.2 Implementation .................................................................................................... 184
10.4 Logic Analyzer Interface (LAI) ..........................................................................................184
10.4.1 Mechanical Considerations.................................................................................. 185
10.4.2 Electrical Considerations ..................................................................................... 185
11 Platform Power Delivery Guidelines ........................................................................................187
11.1 Processor Voltage Regulator Power Delivery Architectural Block Diagram ..................... 188
11.2 Customer Reference Board Power Delivery .....................................................................188
11.2.1 Processor Core Voltage (VCC_CORE) ............................................................... 190
11.2.2 System Bus Voltage (VCCP 1.05 V).................................................................... 190
11.2.3 2.5 V ....................................................................................................................190
11.2.4 1.25 V ..................................................................................................................190
11.2.5 1.8 V ....................................................................................................................191
11.2.6 1.2 V ....................................................................................................................191
11.2.7 5 VSB................................................................................................................... 191
11.2.8 3.3 VSB................................................................................................................ 191
11.2.9 1.8 VSB................................................................................................................ 191
11.2.10 Power Summary .................................................................................................. 191
Design Guide
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Intel Pentium
Bus Topology ....................................................................................... 169
LCI Routing Parameters ...................................................................... 169
General Trace Routing Considerations................................................ 170
Trace Geometry and Length ................................................................171
Signal Isolation..................................................................................... 171
Power and Ground Connections .......................................................... 172
General Power and Ground Plane Consideration................................ 172
Board Design ....................................................................................... 173
Common Physical Layout Issues .........................................................173
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82562ET/Intel 82562EM Guidelines ........................................................ 175
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Intel 82562ET/Intel
Crystals and Oscillators .......................................................................175
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Intel 82562ET/Intel
Distance from Magnetics Module to RJ45 (Distance A) ...................... 177
Distance from Intel® 82562ET to Magnetics Module (Distance B) ...... 177
Termination Plane Capacitance ........................................................... 178
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M Processor Logic Analyzer Support ..................................................... 184
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M Processor and Intel
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82562EM Component Placement Guidelines... 175
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82562EM Termination Resistors ...................... 176
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E7501 Chipset Platform
Contents
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