Table of Contents
Advertisement
®
®
Intel
Pentium
M Processor and Intel
Memory Interface Routing Guidelines
Figure 35.
DIMM Connector Styles Supported
6.3
Dual Channel DDR Overview
In a dual channel DDR configuration, channel A and B are active and operate in lock-step which
logically appears to be one 144-bit wide memory bus; however, each channel is separate
electrically.
Figure 36
'A' and 'B' in the figures refer to the DIMM channel. The number following 'A' or 'B' refers to the
DIMM logical group. The DIMMs are physically interleaved. Intel recommends using this
interleaving, starting with Channel B closest to the MCH, for optimal routing.
The platform requires DDR DIMMs to be populated in-order, starting with the DIMMs furthest
from the MCH in a 'fill-farthest' approach (see
be populated furthest when a combination of single ranked and double ranked DIMMs are used.
This recommendation is based on the signal integrity requirements of the DDR interface. Intel's
recommendation is to check for correct DIMM placement during BIOS initialization. Additionally,
it is strongly recommended that all designs follow the DIMM ordering, SMBus Addressing,
Command Clock routing and Chip Select routing documented in
addressing must be maintained to be compliant with the reference BIOS code supplied by Intel.
76
®
E7501 Chipset Platform
and
Figure 37
show both channels being routed to a single bank of DIMMs. The letters
o
90
MotherBoard
DIMM
o
25
MotherBoard
DIMM
o
0
MotherBoard
Figure
37). In addition, single rank DIMMs should
DIMM
Vertical DIMM Connector
25 deg DIMM Connector
Right Angle DIMM Connector
Figure 36
and
Figure
37. This
Design Guide
Advertisement
Table of Contents
