Smbus Address Considerations; Reference Schematic For Dual-Slot Parallel Mode; Dual-Slot Parallel Smbus Circuit - Intel Pentium M Processor Design Manual

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Intel Pentium M Processor and Intel
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Intel 82870P2 (Intel P64H2)
8.2.8.8

SMBus Address Considerations

In dual-slot parallel mode, the SMBus address strap pins in
control signals HxRESETA# and HxBUSENB#. Therefore, it is recommended that the following
technique be used for determining an SMBus address. Pull the PAGNT5 (RESETA#) signals to
ground through a 100 kΩ ± 5% resistor. This keeps the reset signal active until the Intel
ready for it to become deasserted. Pull the PAGNT4 (BUSENB#) signals to 3.3 V through a
10 kΩ ± 5% resistor. The Intel P64H2 may be able to drive this signal to ground when the signal
must be asserted.
Keep in mind that this limits the range of addresses you may achieve. Using this technique, the
address is fixed when operating in dual-slot parallel mode on both controllers.

dual-slot parallel SMBus circuit.

Figure 100. Dual-Slot Parallel SMBus Circuit
Intel
NOTE: The pin names shown in the Intel
to
8.2.8.9

Reference Schematic for Dual-Slot Parallel Mode

Note that the schematic in
144
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E7501 Chipset Platform
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P64H2
HX_RESETA#
100 kΩ
HX_BUSENA#
HX_RESETB#
3.3V
10 kΩ
HX_BUSENB#
Table 78 for the corresponding Intel P64H2 pin name.
Figure 101
Table 73
Slot 1
Switch
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P64H2 block are slot pin names. For dual-slot parallel mode, refer
is based on definition and simulation of the Intel P64H2.
are multiplexed as Hot-Plug
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P64H2 is
Figure 100 shows a
Slot 2
Switch
Design Guide