Closed Loop Stability - Required; +5V Dc / +3.3V Dc Power Sequencing - Required; Figure 4-2: Power Supply Timing - Intel ATX 3.0 Design Manual

Electrical
4.2.7

Closed Loop Stability - REQUIRED

The power supply shall be unconditionally stable under all line/load/transient load
conditions including capacitive loads specified in
degrees phase margin and 10 dB gain margin is recommended at both the maximum
and minimum loads.
4.2.8

+5V DC / +3.3V DC Power Sequencing - REQUIRED

The +12V1 DC / +12V2 DC and +5 VDC output levels must be equal to or greater
than the +3.3 VDC output at all times during power-up and normal operation. The
time between any output of +12V1 DC / +12V2 DC and +5 VDC reaching its minimum
in-regulation level and +3.3 VDC reaching its minimum in-regulation level must be ≤
20 ms as shown in

Figure 4-2: Power Supply Timing

336521
Output
+5VDC
+3.3VDC
-12VDC
+5VSB
Figure 4-2.
μ
Capacitive Load ( F)
3,300
3,300
330
3,300
Section 4.2.6. A minimum of 45
35