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7.4
Power Sequencing
This section shows the timings between various signals during different power state transitions.
Figure 7-3. G3-S0 Transistion
Cycle 1 from GMCH
Cycle 1 from ICH
Cycle 2 from GMCH
Cycle 2 from ICH
®
Intel
810A3 Chipset Design Guide
Vcc3.3sus
t1
RSMRST#
t2
t3
SLP_S3#
t4
SLP_S5#
t5
SUS_STAT#
Vcc3.3core
CPUSLP#
PWROK
Clocks
PCIRST#
STPCLK#
Freq straps
CPURST#
t6
t7
t8
t9
Clocks invalid
System Design Considerations
Clocks valid
t10
t11
t12
t13
t14
t15
t16
t17
7-9
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