1.8 V And 3.3 V Power Sequence Requirement; Figure 135. Example Power-On 3.3 V / 1.8 V Sequencing Circuit - Intel Pentium 4 Design Manual

I/O Controller Hub 2
9.15

1.8 V and 3.3 V Power Sequence Requirement

The ICH2 has two pairs of associated 1.8 V and 3.3 V supplies. These supplies are Vcc1_8,
Vcc3_3 and VccSus1_8, VccSus3_3. These pairs are assumed to power up and power down
together. The difference between the two associated supplies must never be greater than 2.0 V.
The 1.8 V supply may come up before the 3.3 V supply without violating this rule (though this is
generally not practical in a desktop environment, since the 1.8 V supply is typically derived from
the 3.3 V supply by means of a linear regulator).
One serious consequence of violation of this "2V Rule" is electrical overstress of oxide layers,
possibly resulting in component damage.
The majority of the ICH2 I/O buffers are driven by the 3.3 V supplies, but are controlled by logic
that is powered by the 1.8 V supplies. If the 3.3 V supply powers up first, the I/O buffers will be in
an undefined state until the 1.8 V logic is powered up. Some signals that are defined as "Input-
only" actually have output buffers that are normally disabled, and the ICH2 may unexpectedly
drive these signals if the 3.3 V supply is active while the 1.8 V supply is not.
Figure 135 is an example power-on sequencing circuit that ensures the "2V Rule" is obeyed. This
circuit uses a NPN (Q2) and PNP (Q1) transistor to ensure the 1.8 V supply tracks the 3.3 V
supply. The NPN transistor controls the current through PNP from the 3.3 V supply into the 1.8 V
power plane by varying the voltage at the base of the PNP transistor. By connecting the emitter of
the NPN transistor to the 1.8 V plane, current will not flow from the 3.3 V supply into 1.8 V plane
when the 1.8 V plane reaches 1.8 V.

Figure 135. Example Power-On 3.3 V / 1.8 V Sequencing Circuit

When analyzing systems that may be "marginally compliant" to the 2V Rule, pay close attention to
the behavior of the ICH2's RSMRST# and PWROK signals, since these signals control internal
isolation logic between the various power planes:
• RSMRST# controls isolation between the RTC well and the Resume wells.
• PWROK controls isolation between the Resume wells and Main wells
• LAN_PWROK controls isolation between the LAN wells and the Resume wells
If one of these signals goes high while one of its associated power planes is active and the other is
inactive, a leakage path will exist between the active and inactive power wells. This could result in
high, possibly damaging internal currents.
188
+3.3V
220
470
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Intel Pentium 4 Processor / Intel
+1.8V
220
Q2
Q1
NPN
PNP
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850 Chipset Family Platform Design Guide
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