Power Delivery; Power Sequencing; Intel ® 80331 I/O Processor Bias Voltages - Intel 80331 Design Manual

Power Delivery

There are several different voltage domains needed on the 80331. These include the following
listed in Table
®
Table 76. Intel 80331 I/O Processor Bias Voltages
Voltage Supply
PCI/Miscellaneous
DDRI
DDRII
IOP Core Voltage
Intel XScale
DDRI Vref
DDRII Vref
9.1

Power Sequencing

The 80331 requires that the VCC33 voltage rail be powered up first and then the VCC15. Note that
there are no sequence order requirements for the VCC25 or VCC18 rail. The power down sequence is
the same in the reverse order.
1) VCC33 power up first
2) VCC15 power up second
The VCC33 greater than or equal to (or no less than 0.5V below) VCC15 (absolute voltage value)
at all times during operations, including during system power-up and power-down. In other words,
the following must always be true:
VCC33 >= (VCC15 - 0.5V)
•
This can be accomplished by placing a diode (with a voltage drop < 0.5V) between VCC15
and VCC33. an Anode is connected to VCC15 and a cathode is connected to VCC33.
•
If a voltage regulator solution is used which shunts VCC15 to ground while VCC33 is
powered, the maximum allowable time that VCC15 can be shunted to ground while VCC33 is
fully powered is 20ms.
•
The maximum allowed time between VCC33 and VCC15 ramping is 525ms. There is no
minimum sequencing time requirement.
76:
3.3V
2.5V
1.8V
1.5V
®
core Voltage 1.35V
1.25V
0.9V
Intel® 80331 I/O Processor Design Guide
Voltage
Power Delivery
9
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