General Differential Signals Design Guidelines; Introduction; General Differential Routing Guidelines; General Differential Length Matching Guidelines - Intel Quark SoC X1000 Design Manual

General Differential Signals Design Guidelines—Intel
Appendix A General Differential Signals Design Guidelines
A.1

Introduction

The guidelines in this chapter are to improve routing for differential signals, such as
PCIe* or USB. The signal routing, via placement and bend optimization examples below
apply to all high speed interfaces.
A.2

General Differential Routing Guidelines

• Do not route traces under power connectors, power modules, voltages regulators,
other interface connectors, crystals, oscillators, clock synthesizers, magnetic
devices or ICs that use and/or duplicate clocks. To minimize reflection, Do not
place stubs, test points, test vias on the route. Utilize vias and connector pads as
test points instead. If a stub is unavoidable in the design, the total of all the stubs
on a particular line should not be greater than 200 mils. Simulation may be
required based on the interface.
• It can be helpful for testability to route the TX and RX pairs for a given port on the
same layer and close to each other to help ensure that the pairs share similar
signaling characteristics. If the groups of traces are similar, a measure of RX pair
layout quality can be approximated by using the results from actively testing the TX
pair's signal quality.
• Separate signal traces into similar categories, and route similar signal traces
together (such as routing differential pairs together).
• Keep signals clear of the core logic set. High current transients are produced during
internal state transitions and can be very difficult to filter out.
A.3

General Differential Length Matching Guidelines

A.3.1

Length Matching and Length Formulas

Follow the specific interface length matching guidelines if provided. If not provided, use
the below as a general guideline.
Table A-1. General Differential Pair Length Matching
Within Layer Max Mismatch
Total Length Max Mismatch
The following are the length matching guidelines for differential-pairs:
• Each signal and its complement in a differential-pair should be length matched
whenever possible on a layer-by-layer basis at the point of discontinuity. 'Within-
layer' matching means that differential pairs should be matched within 15mils
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
Description
Routing
Units
Recommendation
mils +/- 15
mils +/- 10
®
Intel Quark™ SoC X1000
PDG
171