5.5.5 Gpmc_Irqenable; Gpmc_Irqenable Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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5.5.5 GPMC_IRQENABLE

The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a
event-by-event basis.
31
15
Reserved
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-10 Reserved
9 WAIT1EDGEDETECTIONENABLE
8 WAIT0EDGEDETECTIONENABLE
7-2 Reserved
1 TERMINALCOUNTEVENTENABLE
0 FIFOEVENTENABLE
SPRUGX9 – 15 April 2011
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Preliminary
Figure 5-55. GPMC_IRQENABLE
10
R-0
2
R-0
Table 5-60. GPMC_IRQENABLE Field Descriptions
Value Description
© 2011, Texas Instruments Incorporated
Reserved
R-0
9
WAIT1EDGE
DETECTIONENABLE
R/W-0
1
TERMINAL
COUNTENABLE
R/W-0
0 Reserved
Enables the Wait1 Edge Detection interrupt
0 Wait1EdgeDetection interrupt is masked
1 Wait1EdgeDetection event generates an interrupt if occurs
Enables the Wait0 Edge Detection interrupt
0 Wait0EdgeDetection interrupt is masked
1 Wait0EdgeDetection event generates an interrupt if occurs
0 Reserved
Enables TerminalCountEvent interrupt issuing in pre-fetch or write
posting mode
0 TerminalCountEvent interrupt is masked
1 TerminalCountEvent interrupt is not masked
Enables the FIFOEvent interrupt
0 FIFOEvent interrupt is masked
1 FIFOEvent interrupt is not masked
General-Purpose Memory Controller (GPMC)
Registers
16
8
WAIT0EDGE
DETECTIONENABLE
R/W-0
0
FIFOEVENT
ENABLE
R/W-0
667