5.5.3 Gpmc_Sysstatus; Gpmc_Sysstatus Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

C6-integra dsp+arm processors
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5.5.3 GPMC_SYSSTATUS

This register provides status information about the module, excluding the interrupt status information.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-1
Reserved
0
RESETDONE
SPRUGX9 – 15 April 2011
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Preliminary
Figure 5-53. GPMC_SYSSTATUS
Reserved
R-0
Table 5-58. GPMC_SYSSTATUS Field Descriptions
Value
Description
0
Reserved
Internal reset monitoring
R0
Internal module reset in on-going
R1
Reset completed
© 2011, Texas Instruments Incorporated
Reserved
R-0
General-Purpose Memory Controller (GPMC)
Registers
16
1
0
RESETDONE
R-0
665

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