Design Recommendations; Stacked Silicon Interconnect - Xilinx 7 Series User Manual

Design Recommendations

Many DSP designs are well suited for the 7 series architecture. To obtain best use of the
architecture, the underlying features and capabilities need to be understood so that design
entry code can take advantage of these resources. DSP48E1 resources are used
automatically for most DSP functions and many arithmetic functions. In most cases, DSP
resources should be inferred. See your preferred synthesis tool documentation for
guidelines to ensure proper inference of the DSP48E1 slice
tools can infer the resources. Instantiation can be used to directly access specific DSP48E1
slice features. Recommendations for using DSP48E1 slices include:
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For more information on design techniques, see
Considerations.

Stacked Silicon Interconnect

The DSP slices cannot be cascaded across the interposer (super logic region (SLR)
boundary). For more information on stacked silicon interconnect (SSI) technology, see
WP380, Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity,
Bandwidth, and Power Efficiency.
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
Use signed values in HDL source
Pipeline for performance and lower power, both in the DSP48E1 slice and fabric
Use the configurable logic block (CLB) carry logic to implement small multipliers,
adders, and counters
Use CLB SRLs, CLB distributed RAM, and/or block RAM to store filter coefficients
Set USE_MULT to NONE when using only the adder/logic unit to save power
Cascade using the dedicated resources rather than fabric, keeping usage to one
column for highest performance and lowest power
Consider using time multiplexing for the design
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Design Recommendations
[Ref 3][Ref 4]. The synthesis
Chapter 3, DSP48E1 Design
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