ST STM32L4 5 Series Reference Manual page 1569

Advanced arm-based 32-bit mcus
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RM0351
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 SDIOITC: SDIOIT flag clear bit
Set by software to clear the SDIOIT flag.
0: SDIOIT not cleared
1: SDIOIT cleared
Bits 21:11 Reserved, must be kept at reset value.
Bit 10 DBCKENDC: DBCKEND flag clear bit
Set by software to clear the DBCKEND flag.
0: DBCKEND not cleared
1: DBCKEND cleared
Bit 9 Reserved, must be kept at reset value.
Bit 8 DATAENDC: DATAEND flag clear bit
Set by software to clear the DATAEND flag.
0: DATAEND not cleared
1: DATAEND cleared
Bit 7 CMDSENTC: CMDSENT flag clear bit
Set by software to clear the CMDSENT flag.
0: CMDSENT not cleared
1: CMDSENT cleared
Bit 6 CMDRENDC: CMDREND flag clear bit
Set by software to clear the CMDREND flag.
0: CMDREND not cleared
1: CMDREND cleared
Bit 5 RXOVERRC: RXOVERR flag clear bit
Set by software to clear the RXOVERR flag.
0: RXOVERR not cleared
1: RXOVERR cleared
Bit 4 TXUNDERRC: TXUNDERR flag clear bit
Set by software to clear TXUNDERR flag.
0: TXUNDERR not cleared
1: TXUNDERR cleared
Bit 3 DTIMEOUTC: DTIMEOUT flag clear bit
Set by software to clear the DTIMEOUT flag.
0: DTIMEOUT not cleared
1: DTIMEOUT cleared
28
27
26
25
Res.
Res.
Res.
12
11
10
9
DBCK
Res.
Res.
ENDC
rw
SD/SDIO/MMC card host interface (SDMMC)
24
23
22
SDIO
Res.
Res.
ITC
rw
8
7
6
CMD
DATA
CMD
REND
ENDC
SENTC
C
rw
rw
rw
DocID024597 Rev 5
21
20
19
Res.
Res.
Res.
5
4
3
RX
TX
DTIME
OVERR
UNDERR
OUTC
C
C
rw
rw
rw
18
17
16
Res.
Res.
Res.
2
1
0
CTIME
DCRC
CCRC
OUTC
FAILC
FAILC
rw
rw
rw
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