Silicon Laboratories C8051F300 Manual
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Silicon Laboratories C8051F300 Manual

Mixed signal isp flash mcu family
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Analog Peripherals
-
8-Bit ADC ('F300/2 only)
Up to 500 ksps
•
Up to 8 external inputs
•
Programmable amplifier gains of 4, 2, 1, & 0.5
•
VREF from external pin or V
•
Built-in temperature sensor
•
External conversion start input
•
-
Comparator
Programmable hysteresis and response time
•
Configurable as interrupt or reset source
•
Low current (<0.5 µA)
•
On-chip Debug
-
On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug (no emulator
required)
-
Provides breakpoints, single stepping,
inspect/modify memory and registers
-
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
-
Complete development kit
Supply Voltage 2.7 to 3.6 V
-
Typical operating current: 6.6 mA @ 25 MHz;
-
Typical stop mode current: 0.1 µA
-
Temperature range: –40 to +85 °C
Rev. 2.9 7/08
DD
14 µA @ 32 kHz
ANALOG
PERIPHERALS
A
M
500 ksps
PGA
U
X
C8051F300/2 only
TEMP
+
SENSOR
-
VOLTAGE COMPARATOR
PROGRAMMABLE PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
8/4/2 kBytes
8051 CPU
ISP Flash
(25MIPS)
12
INTERRUPTS
CIRCUITRY
Copyright © 2008 by Silicon Laboratories
C8051F300/1/2/3/4/5
Mixed Signal ISP Flash MCU Family
High Speed 8051 µc Core
-
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
-
Up to 25 MIPS throughput with 25 MHz clock
-
Expanded interrupt handler
Memory
-
256 bytes internal data RAM
-
Up to 8 kB ('F300/1/2/3), 4 kB ('F304), or 2 kB
('F305) Flash; 512 bytes are reserved in the 8 kB
devices
Digital Peripherals
-
8 Port I/O; All 5 V tolerant with high sink current
-
Hardware enhanced UART and SMBus™ serial
ports
-
Three general-purpose 16-bit counter/timers
-
16-bit programmable counter array (PCA) with three
capture/compare modules
-
Real time clock mode using PCA or timer and
external clock source
Clock Sources
-
Internal oscillator: 24.5 MHz with ±2% accuracy
supports UART operation
-
External oscillator: Crystal, RC, C, or clock (1 or 2
pin modes)
-
Can switch between clock sources on-the-fly; Useful
in power saving modes
11-Pin QFN or 14-Pin SOIC Package
-
QFN Size = 3x3 mm
DIGITAL I/O
UART
8-bit
SMBus
PCA
ADC
Timer 0
Timer 1
Timer 2
256 B SRAM
DEBUG
POR
WDT
C8051F300/1/2/3/4/5

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  • Page 1 C8051F300/2 only TEMP Timer 1 SENSOR Timer 2 VOLTAGE COMPARATOR PROGRAMMABLE PRECISION INTERNAL OSCILLATOR HIGH-SPEED CONTROLLER CORE 8/4/2 kBytes 8051 CPU 256 B SRAM ISP Flash (25MIPS) DEBUG INTERRUPTS CIRCUITRY Rev. 2.9 7/08 Copyright © 2008 by Silicon Laboratories C8051F300/1/2/3/4/5...
  • Page 2 C8051F300/1/2/3/4/5 OTES Rev. 2.9...

  • Page 3: Table Of Contents

    1.4. Programmable Digital I/O and Crossbar ............19 1.5. Serial Ports ....................... 20 1.6. Programmable Counter Array ................21 1.7. 8-Bit Analog to Digital Converter (C8051F300/2 Only) ........22 1.8. Comparator ....................... 23 2. Absolute Maximum Ratings .................. 24 3. Global Electrical Characteristics ................25 4.
  • Page 4 C8051F300/1/2/3/4/5 8.3.4. Interrupt Latency ..................73 8.3.5. Interrupt Register Descriptions..............75 8.4. Power Management Modes ................80 8.4.1. Idle Mode....................80 8.4.2. Stop Mode ....................81 9. Reset Sources......................83 9.1. Power-On Reset ....................84 9.2. Power-Fail Reset/VDD Monitor................. 84 9.3.
  • Page 5 C8051F300/1/2/3/4/5 13.4.Using the SMBus.................... 115 13.4.1.SMBus Configuration Register............... 116 13.4.2.SMB0CN Control Register ..............119 13.4.3.Data Register ..................122 13.5.SMBus Transfer Modes.................. 123 13.5.1.Master Transmitter Mode ............... 123 13.5.2.Master Receiver Mode ................124 13.5.3.Slave Receiver Mode ................125 13.5.4.Slave Transmitter Mode ................. 126 13.6.SMBus Status Decoding.................
  • Page 6 C8051F300/1/2/3/4/5 OTES Rev. 2.9...
  • Page 7 Figure 1.3. Comparison of Peak MCU Execution Speeds ........16 Figure 1.4. On-Chip Clock and Reset ..............17 Figure 1.5. On-chip Memory Map (C8051F300/1/2/3 Shown) ......... 18 Figure 1.6. Development/In-System Debug Diagram..........19 Figure 1.7. Digital Crossbar Diagram ............... 20 Figure 1.8.
  • Page 8 C8051F300/1/2/3/4/5 10. Flash Memory Figure 10.1. Flash Program Memory Map..............91 11. Oscillators Figure 11.1. Oscillator Diagram................97 Figure 11.2. 32.768 kHz External Crystal Example..........101 12. Port Input/Output Figure 12.1. Port I/O Functional Block Diagram ............. 103 Figure 12.2. Port I/O Cell Block Diagram ............... 103 Figure 12.3.
  • Page 9 3. Global Electrical Characteristics Table 3.1. Global Electrical Characteristics ............. 25 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5 ........... 27 Table 4.2. QFN-11 Package Dimensions ..............29 Table 4.3. QFN-11 Landing Diagram Dimensions ........... 31 Table 4.4.
  • Page 10 C8051F300/1/2/3/4/5 Table 14.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator ......... 139 Table 14.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz Oscillator ........... 140 Table 14.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Oscillator .........
  • Page 11 SFR Definition 5.2. ADC0CF: ADC0 Configuration (C8051F300/2) ....43 SFR Definition 5.3. ADC0: ADC0 Data Word (C8051F300/2) ....43 SFR Definition 5.4.
  • Page 12 C8051F300/1/2/3/4/5 SFR Definition 15.4. TL0: Timer 0 Low Byte ....... . 150 SFR Definition 15.5.

  • Page 13: System Overview

    Each device is specified for 2.7 to 3.6 V operation over the industrial temperature range (–45 to +85 °C). The Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051F300/1/2/3/4/5 are available in 3 x 3 mm 11-pin QFN or 14-pin SOIC packaging.

  • Page 14: Table 1.1. Product Selection Guide

    C8051F300/1/2/3/4/5 Table 1.1. Product Selection Guide        C8051F300-GM QFN-11        C8051F300-GS SOIC-14      C8051F301-GM — — QFN-11      C8051F301-GS —...

  • Page 15: Figure 1.1. C8051F300/2 Block Diagram

    Precision Control Internal Oscillator VREF Config. & Temp Clock & Reset Control Configuration 8-bit AIN0-AIN7 500ksps CNVSTR Figure 1.1. C8051F300/2 Block Diagram Analog/Digital Power Port I/O Mode & Config. Port 0 P0.0/VREF Debug HW Latch 8k/4k/2k P0.1 byte UART Reset...

  • Page 16: Microcontroller Core

    CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F300/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052,...

  • Page 17: Additional Features

    The WDT may be permanently enabled in software after a power- on reset during MCU initialization. The internal oscillator is available as a factory calibrated 24.5 MHz ±2% (C8051F300/1 devices); an uncal- ibrated version is available on C8051F302/3/4/5 devices. On all C8051F300/1/2/3/4/5 devices, the internal oscillator period may be user programmed in ~0.5% increments.

  • Page 18: On-Chip Memory

    16 bytes can be byte addressable or bit addressable. The C8051F300/1/2/3 includes 8k bytes of Flash program memory (the C8051F304 includes 4k bytes; the C8051F305 includes 2k bytes). This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage.

  • Page 19: On-Chip Debug Circuitry

    Programmable Digital I/O and Crossbar C8051F300/1/2/3/4/5 devices include a byte-wide I/O Port that behaves like a typical 8051 Port with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output.

  • Page 20: Serial Ports

    Figure 1.7. Digital Crossbar Diagram 1.5. Serial Ports The C8051F300/1/2/3/4/5 Family includes an SMBus/I C interface and a full-duplex UART with enhanced baud rate configuration. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention.

  • Page 21: Programmable Counter Array

    C8051F300/1/2/3/4/5 1.6. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the three 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three pro- grammable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or the external oscillator clock source divided by 8.

  • Page 22: 8-Bit Analog To Digital Converter (C8051F300/2 Only)

    1.7. 8-Bit Analog to Digital Converter (C8051F300/2 Only) The C8051F300/2 includes an on-chip 8-bit SAR ADC with a 10-channel differential input multiplexer and programmable gain amplifier. With a maximum throughput of 500 ksps, the ADC offers true 8-bit accuracy with an INL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects both posi- tive and negative ADC inputs.

  • Page 23: Comparator

    1.8. Comparator C8051F300/1/2/3/4/5 devices include an on-chip voltage comparator that is enabled/disabled and config- ured via user software. All Port I/O pins may be configurated as comparator inputs. Two comparator out- puts may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output.

  • Page 24: Absolute Maximum Ratings

    C8051F300/1/2/3/4/5 Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* Parameter Conditions Units Ambient temperature under bias –55 — °C Storage Temperature –65 — °C Voltage on any Port I/O Pin or RST with respect to –0.3 — Voltage on V with respect to GND –0.3...

  • Page 25: Global Electrical Characteristics

    C8051F300/1/2/3/4/5 Global Electrical Characteristics Table 3.1. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Conditions Units Digital Supply Voltage Digital Supply RAM Data — — Retention Voltage — SYSCLK (System Clock) (Note 2) (SYSCLK High Time) —...
  • Page 26 C8051F300/1/2/3/4/5 Table 3.1. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Conditions Units Supply Sensitivity (Note 3) F = 25 MHz — — F = 1 MHz — — Frequency Sensitivity = 3.0 V, F <= 1 MHz, T = 25 —...

  • Page 27: Pinout And Package Definitions

    C8051F300/1/2/3/4/5 Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5 Name Type Description F300/1/2/3/4/5 F300/1/2/3/4/5 VREF / A In External Voltage Reference Input. P0.0 D I/O or Port 0.0. See Section 12 for complete description. A In P0.1 D I/O or Port 0.1.

  • Page 28: Figure 4.1. Qfn-11 Pinout Diagram (Top View)

    C8051F300/1/2/3/4/5 C2D / VREF / P0.7 P0.0 P0.6 / P0.1 CNVSTR C2CK / /RST XTAL1 / P0.5 P0.2 XTAL2 / P0.4 P0.3 Figure 4.1. QFN-11 Pinout Diagram (Top View) Rev. 2.9...

  • Page 29: Figure 4.2. Qfn-11 Package Drawing

    C8051F300/1/2/3/4/5 Figure 4.2. QFN-11 Package Drawing Table 4.2. QFN-11 Package Dimensions Dimension Dimension 0.80 0.90 1.00 3.00 BSC. 0.03 0.07 0.11 2.20 2.25 2.30 0.25 REF 0.18 0.25 0.30 0.15 3.00 BSC. 0.15 1.30 1.35 1.40 0.05 0.50 BSC. 0.08 Notes: 1.

  • Page 30: Figure 4.3. Typical Qfn-11 Solder Paste Mask

    C8051F300/1/2/3/4/5 0.10 mm 0.35 mm 0.50 mm 0.50 mm 0.30 mm 0.35 mm 0.20 mm 0.30 mm 0.20 mm 0.70 mm 0.60 mm 0.20 mm 0.30 mm Figure 4.3. Typical QFN-11 Solder Paste Mask Rev. 2.9...

  • Page 31: Figure 4.4. Typical Qfn-11 Landing Diagram

    C8051F300/1/2/3/4/5 Figure 4.4. Typical QFN-11 Landing Diagram Table 4.3. QFN-11 Landing Diagram Dimensions Dimension 2.75 2.85 2.75 2.85 0.50 BSC 0.20 0.30 1.40 1.50 0.65 0.75 2.30 2.40 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted.

  • Page 32: Figure 4.5. Soic-14 Pinout Diagram (Top View)

    C8051F300/1/2/3/4/5 TOP VIEW P0.6 C2CK/RST C2D/P0.7 P0.5 P0.4 P0.0 P0.3 P0.1 P0.2 Figure 4.5. SOIC-14 Pinout Diagram (Top View) Rev. 2.9...

  • Page 33: Figure 4.6. Soic-14 Package Drawing

    C8051F300/1/2/3/4/5 Figure 4.6. SOIC-14 Package Drawing Table 4.4. SOIC-14 Package Dimensions Dimension Dimension - - - 1.75 0.40 1.27 0.10 0.25 0.25 BSC 0.33 0.51 0° 8° 0.17 0.25 0.10 8.65 BSC 0.20 6.00 BSC 0.10 3.90 BSC 0.25 1.27 BSC Notes: 1.

  • Page 34: Figure 4.7. Soic-14 Pcb Land Pattern

    C8051F300/1/2/3/4/5 Figure 4.7. SOIC-14 PCB Land Pattern Table 4.5. SOIC-14 PCB Land Pattern Dimensions Dimension 5.30 5.40 1.27 BSC 0.50 0.60 1.45 1.55 Rev. 2.9...

  • Page 35: Adc0 (8-Bit Adc, C8051F300/2)

    C8051F300/1/2/3/4/5 ADC0 (8-Bit ADC, C8051F300/2) The ADC0 subsystem for the C8051F300/2 consists of two analog multiplexers (referred to collectively as AMUX0) with 11 total input selections, a differential programmable gain amplifier (PGA), and a 500 ksps, 8- bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector (see block diagram in Figure 5.1).

  • Page 36: Analog Multiplexer And

    C8051F300/1/2/3/4/5 5.1. Analog Multiplexer and PGA The analog multiplexers (AMUX0) select the positive and negative inputs to the PGA, allowing any Port pin to be measured relative to any other Port pin or GND. Additionally, the on-chip temperature sensor or the positive power supply (V ) may be selected as the positive PGA input.

  • Page 37: Figure 5.2. Typical Temperature Sensor Transfer Function

    C8051F300/1/2/3/4/5 (mV) 1200 1100 1000 = 3.35*(TEMP ) + 897 mV TEMP (Celsius) Figure 5.2. Typical Temperature Sensor Transfer Function The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea- surements (see Table 5.1 for linearity specifications). For absolute temperature measurements, gain and/ or offset calibration is recommended.

  • Page 38: Figure 5.3. Temperature Sensor Error With 1-Point Calibration (Vref = 2.40 V)

    C8051F300/1/2/3/4/5 5.00 5.00 4.00 4.00 3.00 3.00 2.00 2.00 1.00 1.00 0.00 0.00 40.00 -40.00 -20.00 0.00 60.00 80.00 20.00 -1.00 -1.00 -2.00 -2.00 -3.00 -3.00 -4.00 -4.00 -5.00 -5.00 Temperature (degrees C) Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V)

  • Page 39: Modes Of Operation

    C8051F300/1/2/3/4/5 5.3. Modes of Operation ADC0 has a maximum conversion speed of 500 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + 1) for 0 ≤ AD0SC ≤ 31).

  • Page 40: Tracking Modes

    C8051F300/1/2/3/4/5 5.3.2. Tracking Modes According to Table 5.1 on page 47, each ADC0 conversion must be preceded by a minimum tracking time for the converted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and- hold mode. In its default state, the ADC0 input is continuously tracked except when a conversion is in prog- ress.

  • Page 41: Settling Time Requirements

    C8051F300/1/2/3/4/5 5.3.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 or PGA selection is made), a mini- mum tracking time is required before an accurate conversion can be performed. This tracking time is deter- mined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion.
  • Page 42 C8051F300/1/2/3/4/5 SFR Definition 5.1. AMX0SL: AMUX0 Channel Select (C8051F300/2) Reset Value AMX0N3 AMX0N2 AMX0N1 AMX0N0 AMX0P3 AMX0P2 AMX0P1 AMX0P0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBB Bits7–4: AMX0N3–0: AMUX0 Negative Input Selection. Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended mode.
  • Page 43 UNUSED. Read = 0b; Write = don’t care. Bits1–0: AMP0GN1–0: ADC0 Internal Amplifier Gain (PGA). 00: Gain = 0.5 01: Gain = 1 10: Gain = 2 11: Gain = 4 SFR Definition 5.3. ADC0: ADC0 Data Word (C8051F300/2) Reset Value 00000000 Bit7 Bit6 Bit5...
  • Page 44 C8051F300/1/2/3/4/5 SFR Definition 5.4. ADC0CN: ADC0 Control (C8051F300/2) Reset Value AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE8 (bit addressable) Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown.

  • Page 45: Programmable Window Detector

    C8051F300/1/2/3/4/5 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an inter- rupt-driven system, saving code space and CPU bandwidth while delivering faster system response times.

  • Page 46: Window Detector In Differential Mode

    0xFE (-2d) 0xFE (-2d) AD0WINT=1 AD0WINT not affected 0x80 (-128d) 0x80 (-128d) -REF -REF Figure 5.7. ADC Window Compare Examples, Differential Mode SFR Definition 5.5. ADC0GT: ADC0 Greater-Than Data Byte (C8051F300/2) Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1...

  • Page 47: Table 5.1. Adc0 Electrical Characteristics

    C8051F300/1/2/3/4/5 Table 5.1. ADC0 Electrical Characteristics = 3.0 V, VREF = 2.40 V (REFSL = 0), PGA Gain = 1, –40 to +85 °C unless otherwise specified. Parameter Conditions Units DC Accuracy Resolution bits Integral Nonlinearity — ±0.5 ±1 Differential Nonlinearity Guaranteed Monotonic —...
  • Page 48 C8051F300/1/2/3/4/5 OTES Rev. 2.9...

  • Page 49: Voltage Reference (C8051F300/2)

    Port I/O configuration details. The external reference voltage must be within the range 0 ≤ VREF ≤ V On C8051F300/2 devices, the temperature sensor connects to the highest order input of the ADC0 positive input multiplexer (see Section “5.1. Analog Multiplexer and PGA” on page 36 for details).

  • Page 50: Table 6.1. External Voltage Reference Circuit Electrical Characteristics

    C8051F300/1/2/3/4/5 SFR Definition 6.1. REF0CN: Reference Control Register Reset Value — — — — REFSL TEMPE BIASE — 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD1 Bits7–3: UNUSED. Read = 00000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select.

  • Page 51: Comparator0

    C8051F300/1/2/3/4/5 Comparator0 C8051F300/1/2/3/4/5 devices include an on-chip programmable voltage comparator, which is shown in Figure 7.1. Comparator0 offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asynchronous “raw”...

  • Page 52: Figure 7.2. Comparator Hysteresis Plot

    C8051F300/1/2/3/4/5 The output of Comparator0 can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator0 output is available asynchronous or synchronous to the system clock; the asynchronous output is available even in STOP mode (with no system clock active).
  • Page 53 C8051F300/1/2/3/4/5 Comparator0 interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “8.3. Interrupt Handler” on page 72). The CP0FIF flag is set to logic 1 upon a Comparator0 falling-edge interrupt, and the CP0RIF flag is set to logic 1 upon the Comparator0 rising-edge interrupt.
  • Page 54 C8051F300/1/2/3/4/5 SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection Reset Value — — CMX0N1 CMX0N0 — — CMX0P1 CMX0P0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9F Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bits6–4: CMX0N1–CMX0N0: Comparator0 Negative Input MUX Select.

  • Page 55: Table 7.1. Comparator0 Electrical Characteristics

    C8051F300/1/2/3/4/5 Table 7.1. Comparator0 Electrical Characteristics = 3.0 V, –40 to +85 °C unless otherwise specified. Parameter Conditions Units Response Time: CP0+ – CP0– = 100 mV — — Mode 0, Vcm* = 1.5 V CP0+ – CP0– = –100 mV —...
  • Page 56 C8051F300/1/2/3/4/5 OTES Rev. 2.9...

  • Page 57: Microcontroller

    C8051F300/1/2/3/4/5 CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are...

  • Page 58: Instruction Set

    C8051F300/1/2/3/4/5 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles.

  • Page 59: Movx Instruction And Program Memory

    8.1.2. MOVX Instruction and Program Memory The MOVX instruction is typically used to access external data memory (Note: the C8051F300/1/2/3/4/5 does not support external data or program memory). In the CIP-51, the MOVX instruction accesses the on- chip program memory space implemented as re-programmable Flash memory.
  • Page 60 C8051F300/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description Bytes Clock Cycles ANL direct, A AND A to direct byte ANL direct, #data AND immediate to direct byte ORL A, Rn OR Register to A ORL A, direct OR direct byte to A...
  • Page 61 C8051F300/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description Bytes Clock Cycles MOVC A, @A+PC Move code byte relative PC to A MOVX A, @Ri Move external data (8-bit address) to A MOVX @Ri, A Move A to external data (8-bit address)
  • Page 62 C8051F300/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description Bytes Clock Cycles JNZ rel Jump if A does not equal zero CJNE A, direct, rel Compare direct byte to A and jump if not equal CJNE A, #data, rel...

  • Page 63: Memory Organization

    Figure 8.2 and Figure 8.3. 8.2.1. Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F300/1/2/3 implements 8192 bytes of this program memory space as in-system, reprogrammable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x1FFF. Note: 512 bytes (0x1E00 - 0x1FFF) of this memory are reserved for factory use and are not available for user program storage.

  • Page 64: Data Memory

    C8051F300/1/2/3/4/5 8.2.2. Data Memory The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Loca- tions 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers.

  • Page 65: Bit Addressable Locations

    C8051F300/1/2/3/4/5 8.2.4. Bit Addressable Locations In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F.

  • Page 66: Table 8.2. Special Function Register (Sfr) Memory Map

    C8051F300/1/2/3/4/5 Table 8.2. Special Function Register (SFR) Memory Map CPT0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 P0MDIN EIP1 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 RSTSRC XBR0 XBR1 XBR2 IT01CF EIE1 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 REF0CN TMR2CN TMR2RLL TMR2RLH TMR2L TMR2H SMB0CN SMB0CF...
  • Page 67 C8051F300/1/2/3/4/5 Table 8.3. Special Function Registers* (Continued) Register Address Description Page 0xB6 FLSCL Flash Scale 0xA8 Interrupt Enable 0xB8 Interrupt Priority 0xE4 IT01CF INT0/INT1 Configuration Register 0xB3 OSCICL Internal Oscillator Calibration 0xB2 OSCICN Internal Oscillator Control 0xB1 OSCXCN External Oscillator Control...

  • Page 68: Register Descriptions

    C8051F300/1/2/3/4/5 Table 8.3. Special Function Registers* (Continued) Register Address Description Page 0x8D Timer/Counter 1 High 0x8A Timer/Counter 0 Low 0x8B Timer/Counter 1 Low 0x89 TMOD Timer/Counter Mode 0xCB TMR2RLH Timer/Counter 2 Reload High 0xCA TMR2RLL Timer/Counter 2 Reload Low 0xCD...
  • Page 69 C8051F300/1/2/3/4/5 SFR Definition 8.2. DPH: Data Pointer High Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x83 Bits7–0: DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed Flash memory.
  • Page 70 C8051F300/1/2/3/4/5 SFR Definition 8.4. PSW: Program Status Word Reset Value PARITY 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD0 (bit addressable) Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction).
  • Page 71 C8051F300/1/2/3/4/5 SFR Definition 8.5. ACC: Accumulator Reset Value ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE0 (bit addressable) Bits7–0: ACC: Accumulator. This register is the accumulator for arithmetic operations.

  • Page 72: Interrupt Handler

    C8051F300/1/2/3/4/5 8.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 12 interrupt sources with two prior- ity levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt- pending flag(s) located in an SFR.

  • Page 73: External Interrupts

    C8051F300/1/2/3/4/5 8.3.2. External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active low;...

  • Page 74: Table 8.4. Interrupt Summary

    C8051F300/1/2/3/4/5 Table 8.4. Interrupt Summary Interrupt Priority Enable Priority Interrupt Source Vector Order Pending Flag Flag Control N/A N/A Always Reset 0x0000 None Always Enabled Highest External Interrupt 0 (/INT0) 0x0003 IE0 (TCON.1) EX0 (IE.0) PX0 (IP.0) Timer 0 Overflow 0x000B TF0 (TCON.5)

  • Page 75: Interrupt Register Descriptions

    C8051F300/1/2/3/4/5 8.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
  • Page 76 C8051F300/1/2/3/4/5 SFR Definition 8.8. IP: Interrupt Priority Reset Value — — 11000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB8 (bit addressable) Bits7–6: UNUSED. Read = 11b, Write = don't care. Bit5: PT2: Timer 2 Interrupt Priority Control.
  • Page 77 C8051F300/1/2/3/4/5 SFR Definition 8.9. EIE1: Extended Interrupt Enable 1 Reset Value — — ECP0R ECP0F EPCA0 EADC0C EWADC0 ESMB0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE6 Bits7–6: UNUSED. Read = 00b. Write = don’t care.
  • Page 78 C8051F300/1/2/3/4/5 SFR Definition 8.10. EIP1: Extended Interrupt Priority 1 Reset Value — — PCP0R PCP0F PPCA0 PADC0C PWADC0 PSMB0 11000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF6 Bits7–6: UNUSED. Read = 11b. Write = don’t care.
  • Page 79 C8051F300/1/2/3/4/5 SFR Definition 8.11. IT01CF: INT0/INT1 Configuration Reset Value IN1PL IN1SL2 IN1SL1 IN1SL0 IN0PL IN0SL2 IN0SL1 IN0SL0 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE4 Note: Refer to SFR Definition 15.1 for INT0/1 edge- or level-sensitive interrupt selection.

  • Page 80: Power Management Modes

    C8051F300/1/2/3/4/5 8.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter- rupts and timers (except the Missing Clock Detector) are inactive, and the system clock is stopped (analog peripherals remain in their selected states).

  • Page 81: Stop Mode

    C8051F300/1/2/3/4/5 8.4.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc- tion that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital periph- erals are stopped;...
  • Page 82 C8051F300/1/2/3/4/5 OTES Rev. 2.9...

  • Page 83: Reset Sources

    C8051F300/1/2/3/4/5 Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their defined reset values •...

  • Page 84: Power-On Reset

    C8051F300/1/2/3/4/5 9.1. Power-On Reset During powerup, the device is held in a reset state and the RST pin is driven low until V settles above . An additional delay occurs before the device is released from reset; the delay decreases as the V...

  • Page 85: External Reset

    C8051F300/1/2/3/4/5 bit in register RSTSRC. See Figure 9.2 for V monitor timing; note that the reset delay is not incurred after a V monitor reset. See Table 9.2 for electrical characteristics of the V monitor. Important Note: Enabling the V monitor will immediately generate a system reset.

  • Page 86: Flash Error Reset

    C8051F300/1/2/3/4/5 9.7. Flash Error Reset If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This may occur due to any of the following: • A Flash write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a MOVX operation is attempted above the user code space address limit.
  • Page 87 C8051F300/1/2/3/4/5 SFR Definition 9.1. RSTSRC: Reset Source Reset Value — FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF Variable Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xEF (Note: Do not use read-modify-write operations (ORL, ANL) on this register) Bit7: UNUSED.
  • Page 88 C8051F300/1/2/3/4/5 OTES Rev. 2.9...

  • Page 89: Flash Memory

    C8051F300/1/2/3/4/5 10. Flash Memory On-chip, reprogrammable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft- ware using the MOVX instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1.

  • Page 90: Flash Write Procedure

    C8051F300/1/2/3/4/5 10.1.3. Flash Write Procedure Flash bytes are programmed by software with the following sequence: Step 1. Disable interrupts (recommended). Step 2. Erase the 512-byte Flash page containing the target location, as described in Section 10.1.2. Step 3. Set the PSWE bit in PSCTL.

  • Page 91: Figure 10.1. Flash Program Memory Map

    C8051F300/1/2/3/4/5 Table 10.2. Security Byte Decoding Bits Description 7–4 Write Lock: Clearing any of these bits to logic 0 prevents all Flash memory from being written or page-erased across the C2 interface 3–0 Read/Write Lock: Clearing any of these bits to logic 0 prevents all Flash memory from being read, written, or page-erased across the C2 interface.
  • Page 92 C8051F300/1/2/3/4/5 Accessing Flash from user firmware executing from an unlocked page: 1. Any unlocked page except the page containing the Lock Byte may be read, written, or erased. 2. Locked pages cannot be read, written, or erased. An erase attempt on the page containing the Lock Byte will result in a Flash Error device reset.
  • Page 93 C8051F300/1/2/3/4/5 SFR Definition 10.2. FLKEY: Flash Lock and Key Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB7 Bits7–0: FLKEY: Flash Lock and Key Register Write: This register must be written to before Flash writes or erases can be performed. Flash remains locked until this register is written to with the following key codes: 0xA5, 0xF1.

  • Page 94: Flash Write And Erase Guidelines

    Code examples showing this can be found in “AN201: Writing to Flash from Firmware", available from the Silicon Laboratories web site. 4. As an added precaution, explicitly enable the V monitor and enable the V monitor as a reset source inside the functions that write and erase Flash memory.

  • Page 95: System Clock

    The external oscillator can continue to run, and the CPU can switch back to the external oscillator after the Flash operation has completed. Additional Flash recommendations and example code can be found in AN201, "Writing to Flash from Firm- ware", available from the Silicon Laboratories web site. Rev. 2.9...
  • Page 96 C8051F300/1/2/3/4/5 OTES Rev. 2.9...

  • Page 97: Oscillators

    The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 11.1. On C8051F300/1 devices, OSCICL is factory calibrated to obtain a 24.5 MHz frequency. On C8051F302/3/4/5 devices, the oscillator frequency is a nominal 20 MHz and may vary ±20% from device-to-device.
  • Page 98 Bits 6–0: OSCICL: Internal Oscillator Calibration Register. This register calibrates the internal oscillator period. The reset value for OSCICL defines the internal oscillator base frequency. On C8051F300/1 devices, the reset value is factory cali- brated to generate an internal oscillator frequency of 24.5 MHz.

  • Page 99: External Oscillator Drive Circuit

    C8051F300/1/2/3/4/5 Table 11.1. Internal Oscillator Electrical Characteristics –40 to +85 °C unless otherwise specified Parameter Conditions Units C8051F300/1 devices 24.5 Calibrated Internal Oscillator –40 to +85 °C Frequency C8051F300/1 devices 24.3 24.7 0 to +70 °C Uncalibrated Internal Oscillator C8051F302/3/4/5 devices...
  • Page 100 C8051F300/1/2/3/4/5 SFR Definition 11.3. OSCXCN: External Oscillator Control Reset Value XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 — XFCN2 XFCN1 XFCN0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB1 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable.

  • Page 101: External Crystal Example

    C8051F300/1/2/3/4/5 11.4. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 11.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in SFR Definition 11.3 (OSCXCN register).

  • Page 102: External Rc Example

    C8051F300/1/2/3/4/5 11.5. External RC Example If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 11.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout.

  • Page 103: Port Input/Output

    C8051F300/1/2/3/4/5 12. Port Input/Output Digital and analog resources are available through a byte-wide digital I/O Port, Port0. Each of the Port pins can be defined as general-purpose I/O (GPIO), analog input, or assigned to one of the internal digital resources as shown in Figure 12.3. The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins.

  • Page 104: Priority Crossbar Decoder

    C8051F300/1/2/3/4/5 12.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 12.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least significant unassigned Port pin is assigned to that resource (excluding UART0, which is always at pins 4 and 5).

  • Page 105: Figure 12.4. Crossbar Priority Decoder With Xbr0 = 0X44

    C8051F300/1/2/3/4/5 SF Signals VREF CNVSTR PIN I/O CP0A SYSCLK CEX0 CEX1 CEX2 XBR0[0:7] Port pin potentially available to peripheral Port pin skipped by CrossBar Special Function Signals are not assigned by the crossbar. When SF Signals these signals are enabled, the CrossBar must be manually configured to skip their corresponding port pins.

  • Page 106: Port I/O Initialization

    C8051F300/1/2/3/4/5 12.2. Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port0 Input Mode register (P0MDIN). Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port0 Output Mode register (P0MDOUT).
  • Page 107 C8051F300/1/2/3/4/5 SFR Definition 12.1. XBR0: Port I/O Crossbar Register 0 Reset Value — XSKP6 XSKP5 XSKP4 XSKP3 XSKP2 XSKP1 XSKP0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE1 Bit7: UNUSED. Read = 0b; Write = don’t care.

  • Page 108: General Purpose Port I/O

    C8051F300/1/2/3/4/5 SFR Definition 12.3. XBR2: Port I/O Crossbar Register 2 Reset Value WEAKPUD XBARE — — — ECIE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE3 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as push-pull).
  • Page 109 C8051F300/1/2/3/4/5 SFR Definition 12.4. P0: Port0 Register Reset Value P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x80 (bit addressable) Bits7–0: P0.[7:0] Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers 0: Logic Low Output.

  • Page 110: Table 12.1. Port I/O Dc Electrical Characteristics

    C8051F300/1/2/3/4/5 SFR Definition 12.6. P0MDOUT: Port0 Output Mode Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA4 Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic 0.

  • Page 111: Smbus

    C8051F300/1/2/3/4/5 13. SMBus The SMBus I/O interface is a two-wire bidirectional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I C serial bus. Reads and writes to the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data.

  • Page 112: Supporting Documents

    C8051F300/1/2/3/4/5 13.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: 1. The I C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I C-Bus Specification – Version 2.0, Philips Semiconductor.

  • Page 113: Arbitration

    C8051F300/1/2/3/4/5 The direction bit (R/W) occupies the least significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit.

  • Page 114: Clock Low Extension

    C8051F300/1/2/3/4/5 13.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency.

  • Page 115: Using The Smbus

    C8051F300/1/2/3/4/5 13.4. Using the SMBus The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con- trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides the following application-independent features: •...

  • Page 116: Smbus Configuration Register

    C8051F300/1/2/3/4/5 13.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit.

  • Page 117: Figure 13.4. Typical Smbus Scl Generation

    C8051F300/1/2/3/4/5 Timer Source Overflows SCL High Timeout High Figure 13.4. Typical SMBus SCL Generation Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
  • Page 118 C8051F300/1/2/3/4/5 SFR Definition 13.1. SMB0CF: SMBus Clock/Configuration Reset Value ENSMB BUSY EXTHOLD SMBTOE SMBFTE SMBCS1 SMBCS0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC1 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins.

  • Page 119: Smb0Cn Control Register

    C8051F300/1/2/3/4/5 13.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 13.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines.
  • Page 120 C8051F300/1/2/3/4/5 SFR Definition 13.2. SMB0CN: SMBus Control Reset Value MASTER TXMODE ACKRQ ARBLOST 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC0 (bit addressable) Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master.

  • Page 121: Table 13.3. Sources For Hardware Changes To Smb0Cn

    C8051F300/1/2/3/4/5 Table 13.3. Sources for Hardware Changes to SMB0CN Set by Hardware When: Cleared by Hardware When: • A START is generated. • A STOP is generated. MASTER • Arbitration is lost. • START is generated. • A START is detected.

  • Page 122: Data Register

    C8051F300/1/2/3/4/5 13.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register.

  • Page 123: Smbus Transfer Modes

    C8051F300/1/2/3/4/5 13.5. SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in Master Mode until it loses arbitration or generates a STOP.

  • Page 124: Master Receiver Mode

    C8051F300/1/2/3/4/5 13.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direc- tion bit.

  • Page 125: Slave Receiver Mode

    C8051F300/1/2/3/4/5 13.5.3. Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit (WRITE in this case) is received.

  • Page 126: Slave Transmitter Mode

    C8051F300/1/2/3/4/5 13.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received.

  • Page 127: Smbus Status Decoding

    C8051F300/1/2/3/4/5 13.6. SMBus Status Decoding The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the shown response options are only the typical responses; application-specific procedures are allowed as long as they conform with the SMBus specification.
  • Page 128 C8051F300/1/2/3/4/5 Table 13.4. SMBus Status Decoding (Continued) Values Read Current SMbus State Typical Response Options Values Written 1000 X A master data byte was received; Acknowledge received byte; ACK requested. Read SMB0DAT. Send NACK to indicate last byte, and send STOP.
  • Page 129 C8051F300/1/2/3/4/5 Table 13.4. SMBus Status Decoding (Continued) Values Read Current SMbus State Typical Response Options Values Written 0010 X A slave address was received; Acknowledge received ACK requested. address (received slave address match, R/W bit = READ). Do not acknowledge received address.
  • Page 130 C8051F300/1/2/3/4/5 OTES Rev. 2.9...

  • Page 131: Uart0

    C8051F300/1/2/3/4/5 14. UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details Section “14.1. Enhanced Baud Rate Generation” on page 132).

  • Page 132: Enhanced Baud Rate Generation

    C8051F300/1/2/3/4/5 14.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 14.2), which is not user accessible.

  • Page 133: Operational Modes

    C8051F300/1/2/3/4/5 14.2. Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below. RS-232 RS-232 C8051Fxxx LEVEL XLTR C8051Fxxx Figure 14.3. UART Interconnect Diagram 14.2.1.

  • Page 134: 9-Bit Uart

    C8051F300/1/2/3/4/5 14.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software.

  • Page 135: Multiprocessor Communications

    C8051F300/1/2/3/4/5 14.3. Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic 1;...
  • Page 136 C8051F300/1/2/3/4/5 SFR Definition 14.1. SCON0: Serial Port 0 Control Reset Value S0MODE — MCE0 REN0 TB80 RB80 01000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x98 (bit addressable) Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode.
  • Page 137 C8051F300/1/2/3/4/5 SFR Definition 14.2. SBUF0: Serial (UART0) Port Data Buffer Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x99 Bits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB-LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmis- sion.

  • Page 138: Table 14.1. Timer Settings For Standard Baud Rates Using The Internal 24.5 Mhz Oscillator

    C8051F300/1/2/3/4/5 Table 14.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator Frequency: 24.5 MHz Target Baud Rate Oscillator Timer Clock SCA1–SCA0 Timer 1 % Error Divide Source Reload Baud Rate (pre-scale Value (hex) (bps) Factor select) 230400 –0.32%...

  • Page 139: Table 14.3. Timer Settings For Standard Baud Rates Using An External 22.1184 Mhz Oscillator

    C8051F300/1/2/3/4/5 Table 14.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator Frequency: 22.1184 MHz Target Baud Rate Oscillator Timer Clock SCA1–SCA0 Timer 1 % Error Divide Source Reload Baud Rate (pre-scale Value (hex) (bps) Factor select) 230400 0.00%...

  • Page 140: Table 14.4. Timer Settings For Standard Baud Rates Using An External 18.432 Mhz Oscillator

    C8051F300/1/2/3/4/5 Table 14.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz Oscillator Frequency: 18.432 MHz Target Baud Rate Oscillator Timer Clock SCA1–SCA0 Timer 1 % Error Divide Source Reload Baud Rate (pre-scale Value (hex) (bps) Factor select) 230400 0.00%...

  • Page 141: Table 14.5. Timer Settings For Standard Baud Rates Using An External 11.0592 Mhz Oscillator

    C8051F300/1/2/3/4/5 Table 14.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Oscillator Frequency: 11.0592 MHz Target Baud Rate Oscillator Timer Clock SCA1-SCA0 Timer 1 % Error Divide Source Reload Baud Rate (pre-scale Value (hex) (bps) Factor select) 230400 0.00%...

  • Page 142: Table 14.6. Timer Settings For Standard Baud Rates Using An External 3.6864 Mhz Oscillator

    C8051F300/1/2/3/4/5 Table 14.6. Timer Settings for Standard Baud Rates Using an External 3.6864 MHZ Oscillator Frequency: 3.6864 MHz Target Baud Rate Oscillator Timer Clock SCA1–SCA0 Timer 1 % Error Divide Source Reload Baud Rate (pre-scale Value (hex) (bps) Factor select) 230400 0.00%...

  • Page 143: Timers

    C8051F300/1/2/3/4/5 15. Timers Each MCU includes 3 counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and one is a 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests.

  • Page 144: Figure 15.1. T0 Mode 0 Block Diagram

    C8051F300/1/2/3/4/5 The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section “12.1. Priority Crossbar Decoder” on page 104 for information on selecting and configuring external I/O pins).

  • Page 145: Mode 1: 16-Bit Counter/Timer

    C8051F300/1/2/3/4/5 15.1.2. Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.

  • Page 146: Mode 3: Two 8-Bit Counter/Timers (Timer 0 Only)

    C8051F300/1/2/3/4/5 15.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0.
  • Page 147 C8051F300/1/2/3/4/5 SFR Definition 15.1. TCON: Timer Control Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x88 (bit addressable) Bit7: TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto- matically cleared when the CPU vectors to the Timer 1 interrupt service routine.
  • Page 148 C8051F300/1/2/3/4/5 SFR Definition 15.2. TMOD: Timer Mode Reset Value GATE1 C/T1 T1M1 T1M0 GATE0 C/T0 T0M1 T0M0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x89 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level.
  • Page 149 C8051F300/1/2/3/4/5 SFR Definition 15.3. CKCON: Clock Control Reset Value — T2MH T2ML — SCA1 SCA0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8E Bit7: UNUSED. Read = 0b, Write = don’t care. Bit6: T2MH: Timer 2 High Byte Clock Select This bit selects the clock supplied to the Timer 2 high byte if Timer 2 is configured in split 8- bit timer mode.
  • Page 150 C8051F300/1/2/3/4/5 SFR Definition 15.4. TL0: Timer 0 Low Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8A Bits 7–0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0 SFR Definition 15.5.

  • Page 151: Timer 2

    C8051F300/1/2/3/4/5 15.2. Timer 2 Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines the Timer 2 operation mode.

  • Page 152: 8-Bit Timers With Auto-Reload

    C8051F300/1/2/3/4/5 15.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 15.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H.
  • Page 153 C8051F300/1/2/3/4/5 SFR Definition 15.8. TMR2CN: Timer 2 Control Reset Value TF2H TF2L TF2LEN — T2SPLIT — T2XCLK 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC8 (bit addressable) Bit7: TF2H: Timer 2 High Byte Overflow Flag Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000.
  • Page 154 C8051F300/1/2/3/4/5 SFR Definition 15.9. TMR2RLL: Timer 2 Reload Register Low Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xCA Bits 7–0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2.

  • Page 155: Programmable Counter Array

    C8051F300/1/2/3/4/5 16. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the Crossbar to Port I/O when enabled (See Section “12.1.

  • Page 156: Pca Counter/Timer

    C8051F300/1/2/3/4/5 16.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.

  • Page 157: Capture/Compare Modules

    C8051F300/1/2/3/4/5 16.2. Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-bit Pulse Width Modulator, or 16-bit Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP- 51 system controller.

  • Page 158: Edge-Triggered Capture Mode

    C8051F300/1/2/3/4/5 16.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/ timer and copy it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge).

  • Page 159: Software Timer (Compare) Mode

    C8051F300/1/2/3/4/5 16.2.2. Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software.

  • Page 160: High Speed Output Mode

    C8051F300/1/2/3/4/5 16.2.3. High Speed Output Mode In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High- Speed Output mode.

  • Page 161: Frequency Output Mode

    C8051F300/1/2/3/4/5 16.2.4. Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out- put is toggled. The frequency of the square wave is then defined by Equation 16.1.

  • Page 162: 8-Bit Pulse Width Modulator Mode

    C8051F300/1/2/3/4/5 16.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated (PWM) output on its associ- ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register.

  • Page 163: 16-Bit Pulse Width Modulator Mode

    C8051F300/1/2/3/4/5 16.2.6. 16-Bit Pulse Width Modulator Mode A PCA module may also be operated in 16-bit PWM mode. In this mode, the 16-bit capture/compare mod- ule defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the output on CEXn is set to ‘1’;...

  • Page 164: Watchdog Timer Mode

    C8051F300/1/2/3/4/5 16.3. Watchdog Timer Mode A programmable watchdog timer (WDT) function is available through the PCA Module 2. The WDT is used to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified limit.

  • Page 165: Watchdog Timer Usage

    C8051F300/1/2/3/4/5 Note that the 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed.

  • Page 166: Table 16.3. Watchdog Timer Timeout Intervals

    C8051F300/1/2/3/4/5 Table 16.3. Watchdog Timer Timeout Intervals System Clock (Hz) PCA0CPL2 Timeout Interval (ms) 24,500,000 32.1 24,500,000 16.2 24,500,000 18,432,000 42.7 18,432,000 21.5 18,432,000 11,059,200 71.1 11,059,200 35.8 11,059,200 3,062,500 3,062,500 129.5 3,062,500 33.1 32,000 24576 32,000 12384 32,000 3168 Notes: 1.

  • Page 167: Register Descriptions For Pca

    C8051F300/1/2/3/4/5 16.4. Register Descriptions for PCA Following are detailed descriptions of the special function registers related to the operation of the PCA. SFR Definition 16.1. PCA0CN: PCA Control Reset Value — — — CCF2 CCF1 CCF0 00000000 Bit7 Bit6 Bit5...
  • Page 168 C8051F300/1/2/3/4/5 SFR Definition 16.2. PCA0MD: PCA Mode Reset Value CIDL WDTE WDLCK — CPS2 CPS1 CPS0 01000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD9 Bit7: CIDL: PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode.
  • Page 169 C8051F300/1/2/3/4/5 SFR Definition 16.3. PCA0CPMn: PCA Capture/Compare Mode Reset Value PWM16n ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xDA, 0xDB, 0xDC PCA0CPMn Address: PCA0CPM0 = 0xDA (n = 0)
  • Page 170 C8051F300/1/2/3/4/5 SFR Definition 16.4. PCA0L: PCA Counter/Timer Low Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF9 Bits 7–0: PCA0L: PCA Counter/Timer Low Byte. The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
  • Page 171 C8051F300/1/2/3/4/5 SFR Definition 16.6. PCA0CPLn: PCA Capture Module Low Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xFB, 0xE9, 0xEB PCA0CPLn Address: PCA0CPL0 = 0xFB (n = 0) PCA0CPL1 = 0xE9 (n = 1) PCA0CPL2 = 0xEB (n = 2) Bits7–0: PCA0CPLn: PCA Capture Module Low Byte.
  • Page 172 C8051F300/1/2/3/4/5 OTES Rev. 2.9...

  • Page 173: C2 Interface

    C8051F300/1/2/3/4/5 17. C2 Interface C8051F300/1/2/3/4/5 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash programming and in-system debugging with the production part installed in the end application. The C2 interface operates using only two pins: a bi-directional data signal (C2D) and a clock input (C2CK). See the C2 Interface Specification for details on the C2 protocol.
  • Page 174 C8051F300/1/2/3/4/5 C2 Register Definition 17.3. REVID: C2 Revision ID Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 This read-only register returns the 8-bit revision ID: 0x00 (Revision A) C2 Register Definition 17.4. FPCTL: C2 Flash Programming Control...

  • Page 175: C2 Pin Sharing

    C8051F300/1/2/3/4/5 17.2. C2 Pin Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and Flash programming functions may be performed. This is possible because C2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled.

  • Page 176: Document Change List

    C8051F300/1/2/3/4/5 Revision 2.5 to Revision 2.6 OCUMENT HANGE • Updated Table 1.1 Product Selection Guide to Revision 2.3 to Revision 2.4 include Lead-free information. • Removed preliminary tag. Revision 2.6 to Revision 2.7 • Changed all references of MLP package to QFN package.
  • Page 177 C8051F300/1/2/3/4/5 OTES Rev. 2.9...

  • Page 178: Contact Information

    The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death.

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