Silicon Laboratories EFM32JG1 Manuals

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Silicon Laboratories EFM32JG1 Reference Manual (953 pages)

EFM32 Jade Gecko Family

Brand: Silicon Laboratories | Category: Microcontrollers | Size: 8 MB

Table of Contents

929
- 1 About this Document
  
  2
  - Introduction
    2
  - Conventions
    3
  - Related Documentation
    4
- 2 System Overview
  
  5
  - Introduction
    5
  - Block Diagrams
    6
  - MCU Features Overview
    7
  - Oscillators and Clocks
    8
  - Hardware CRC Support
    8
  - Data Encryption and Authentication
    9
  - Timers
    10
- 3 System Processor
  
  11
  - Introduction
    11
  - Features
    12
  - Functional Description
    12
  - Interrupt Operation
    13
  - Avoiding Extraneous Interrupts
    13
  - IFC Read-Clear Operation
    13
  - Interrupt Request Lines (IRQ)
    14
- 4 Memory and Bus System
  
  15
- 5 DBG - Debug Interface
  
  62
  - Introduction
    62
  - Features
    62
  - Functional Description
    62
  - Debug Pins
    63
  - Debug and EM2 Deepsleep/Em3 Stop
    63
  - Authentication Access Point
    63
  - Command Key
    63
  - Device Erase
    63
  - System Reset
    63
  - System Bus Stall
    63
  - User Flash
    63
  - Debug Lock
    64
  - AAP Lock
    64
  - Debugger Reads of Actionable Registers
    64
  - Debug Recovery
    65
  - Register Map
    65
  - Register Description
    65
  - AAP_CMD - Command Register
    65
  - AAP_CMDKEY - Command Key Register
    66
  - AAP_STATUS - Status Register
    66
  - AAP_CTRL - Control Register
    67
  - AAP_CRCCMD - CRC Command Register
    67
  - AAP_CRCSTATUS - CRC Status Register
    68
  - AAP_CRCADDR - CRC Address Register
    68
  - AAP_CRCRESULT - CRC Result Register
    69
  - AAP_IDR - AAP Identification Register
    69
- 6 MSC - Memory System Controller
  
  70
  - Introduction
    70
  - Features
    71
  - Functional Description
    72
  - User Data (UD)
    72
  - Lock Bits (LB)
    73
  - Device Information (DI) Page
    73
  - Bootloader
    73
  - Device Revision
    74
  - Post-Reset Behavior
    74
  - Flash Startup
    74
  - Wait-States
    75
  - One Wait-State Access
    75
  - Zero Wait-State Access
    75
  - Operation above
    75
  - Suppressed Conditional Branch Target Prefetch (SCBTP)
    75
  - Cortex-M3 If-Then Block Folding
    75
  - Instruction Cache
    76
  - Erase and Write Operations
    77
  - Mass Erase
    77
  - Register Map
    78
  - Register Description
    79
  - MSC_CTRL - Memory System Control Register
    79
  - MSC_READCTRL - Read Control Register
    80
  - MSC_WRITECTRL - Write Control Register
    82
  - MSC_WRITECMD - Write Command Register
    83
  - MSC_ADDRB - Page Erase/Write Address Buffer
    84
  - MSC_WDATA - Write Data Register
    84
  - MSC_STATUS - Status Register
    85
  - MSC_IF - Interrupt Flag Register
    86
  - MSC_IFS - Interrupt Flag Set Register
    87
  - MSC_IFC - Interrupt Flag Clear Register
    88
  - MSC_IEN - Interrupt Enable Register
    89
  - MSC_LOCK - Configuration Lock Register
    90
  - MSC_CACHECMD - Flash Cache Command Register
    91
  - MSC_CACHEHITS - Cache Hits Performance Counter
    91
  - MSC_CACHEMISSES - Cache Misses Performance Counter
    92
  - MSC_MASSLOCK - Mass Erase Lock Register
    92
  - MSC_STARTUP - Startup Control
    93
  - MSC_CMD - Command Register
    94
- 7 LDMA - Linked DMA Controller
  
  95
  - Introduction
    95
  - Features
    96
  - Block Diagram
    97
  - Functional Description
    98
  - Channel Descriptor
    98
  - DMA Transfer Size
    98
  - Source/Destination Increments
    98
  - Block Size
    98
  - Transfer Count
    99
  - Descriptor List
    99
  - Addresses
    99
  - Addressing Modes
    99
  - Byte Swap
    100
  - DMA Size and Source/Destination Increment Programming
    101
  - Channel Configuration
    103
  - Address Increment/Decrement
    103
  - Loop Counter
    103
  - Channel Select Configuration
    103
  - Starting a Transfer
    103
  - Peripheral Transfer Requests
    104
  - Managing Transfer Errors
    104
  - Arbitration
    104
  - Arbitration Priority
    104
  - DMA Transfer Arbitration
    106
  - Channel Descriptor Data Structure
    107
  - XFER Descriptor Structure
    107
  - SYNC Descriptor Structure
    108
  - WRI Descriptor Structure
    109
  - Interaction with the EMU
    109
  - Interrupts
    110
  - Debugging
    110
  - Examples
    110
  - Single Direct Register DMA Transfer
    110
  - Descriptor Linked List
    111
  - Single Descriptor Looped Transfer
    113
  - Descriptor List with Looping
    114
  - Simple Inter-Channel Synchronization
    115
  - Copy
    117
  - Ping-Pong
    119
  - Scatter-Gather
    120
  - Register Map
    121
  - Register Description
    122
  - LDMA_CTRL - DMA Control Register
    122
  - LDMA_STATUS - DMA Status Register
    123
  - LDMA_SYNC - DMA Synchronization Trigger Register (Single-Cycle RMW)
    124
  - LDMA_CHEN - DMA Channel Enable Register (Single-Cycle RMW)
    124
  - LDMA_CHBUSY - DMA Channel Busy Register
    125
  - LDMA_CHDONE - DMA Channel Linking Done Register (Single-Cycle RMW)
    125
  - LDMA_DBGHALT - DMA Channel Debug Halt Register
    126
  - LDMA_SWREQ - DMA Channel Software Transfer Request Register
    126
  - LDMA_REQDIS - DMA Channel Request Disable Register
    127
  - LDMA_REQPEND - DMA Channel Requests Pending Register
    127
  - LDMA_LINKLOAD - DMA Channel Link Load Register
    128
  - LDMA_REQCLEAR - DMA Channel Request Clear Register
    128
  - LDMA_IF - Interrupt Flag Register
    129
  - LDMA_IFS - Interrupt Flag Set Register
    129
  - LDMA_IFC - Interrupt Flag Clear Register
    130
  - LDMA_IEN - Interrupt Enable Register
    130
  - Ldma_Chx_Reqsel - Channel Peripheral Request Select Register
    131
  - Ldma_Chx_Cfg - Channel Configuration Register
    134
  - Ldma_Chx_Loop - Channel Loop Counter Register
    135
  - Ldma_Chx_Ctrl - Channel Descriptor Control Word Register
    136
  - Ldma_Chx_Src - Channel Descriptor Source Data Address Register
    139
  - Ldma_Chx_Dst - Channel Descriptor Destination Data Address Register
    140
  - Ldma_Chx_Link - Channel Descriptor Link Structure Address Register
    141
- 8 RMU - Reset Management Unit
  
  142
  - Introduction
    142
  - Features
    142
  - Functional Description
    143
  - Reset Levels
    144
  - RMU_RSTCAUSE Register
    145
  - Power-On Reset (POR)
    146
  - Brown-Out Detector (BOD)
    146
  - Resetn Pin Reset
    147
  - Watchdog Reset
    147
  - Lockup Reset
    147
  - System Reset Request
    147
  - Reset State
    147
  - Registers with Alternate Reset
    147
  - Registers with Alternate Reset
    148
  - Register Map
    149
  - Register Description
    150
  - RMU_CTRL - Control Register
    150
  - RMU_RSTCAUSE - Reset Cause Register
    153
  - RMU_CMD - Command Register
    155
  - RMU_RST - Reset Control Register
    155
  - RMU_LOCK - Configuration Lock Register
    156
- 9 EMU - Energy Management Unit
  
  157
  - Introduction
    157
  - Features
    157
  - Functional Description
    158
  - Energy Modes
    159
  - EM0 Active
    160
  - EM1 Sleep
    160
  - EM2 Deepsleep
    161
  - EM3 Stop
    161
  - EM4 Hibernate
    161
  - EM4 Shutoff
    162
  - Entering Low Energy Modes
    162
  - Entry into EM1 Sleep
    162
  - Entry into EM2 Deepsleep or EM3 Stop
    162
  - Entry into EM4 Hibernate
    162
  - Exiting a Low Energy Mode
    163
  - Power Configurations
    164
  - Power Configuration 0: STARTUP
    165
  - Power Configuration 1: no DC-DC
    166
  - Power Configuration 2: DC-DC
    167
  - DC-To-DC Interface
    167
  - Bypass Mode
    168
  - Low Power (LP) Mode
    168
  - Low Noise (LN) Mode
    168
  - Analog Peripheral Power Selection
    169
  - IOVDD Connection
    169
  - DC-To-DC Programming Guidelines
    169
  - Brown out Detector (BOD)
    169
  - Avdd Bod
    169
  - DVDD and DECOUPLE BOD
    169
  - Voltage Monitor (VMON)
    170
  - Powering off SRAM Blocks
    170
  - Temperature Sensor Status
    170
  - Registers Latched in EM4
    170
  - Register Resets
    170
  - Register Map
    171
  - Register Description
    172
  - EMU_CTRL - Control Register
    172
  - EMU_STATUS - Status Register
    173
  - EMU_LOCK - Configuration Lock Register
    174
  - EMU_RAM0CTRL - Memory Control Register
    175
  - EMU_CMD - Command Register
    176
  - EMU_EM4CTRL - EM4 Control Register
    177
  - EMU_TEMPLIMITS - Temperature Limits for Interrupt Generation
    178
  - EMU_TEMP - Value of Last Temperature Measurement
    178
  - EMU_IF - Interrupt Flag Register
    179
  - EMU_IFS - Interrupt Flag Set Register
    182
  - EMU_IFC - Interrupt Flag Clear Register
    185
  - EMU_IEN - Interrupt Enable Register
    188
  - EMU_PWRLOCK - Regulator and Supply Lock Register
    190
  - EMU_PWRCFG - Power Configuration Register. this Is no Longer Used
    191
  - EMU_PWRCTRL - Power Control Register
    191
  - EMU_DCDCCTRL - DCDC Control
    192
  - EMU_DCDCMISCCTRL - DCDC Miscellaneous Control Register
    193
  - EMU_DCDCZDETCTRL - DCDC Power Train NFET Zero Current Detector Control Register
    195
  - EMU_DCDCCLIMCTRL - DCDC Power Train PFET Current Limiter Control Register
    196
  - EMU_DCDCLNVCTRL - DCDC Low Noise Voltage Register
    197
  - EMU_DCDCTIMING - DCDC Controller Timing Value Register
    198
  - EMU_DCDCLPVCTRL - DCDC Low Power Voltage Register
    199
  - EMU_DCDCLPCTRL - DCDC Low Power Control Register
    200
  - EMU_DCDCLNFREQCTRL - DCDC Low Noise Controller Frequency Control
    201
  - EMU_DCDCSYNC - DCDC Read Status Register
    201
  - EMU_VMONAVDDCTRL - VMON AVDD Channel Control
    202
  - EMU_VMONALTAVDDCTRL - Alternate VMON AVDD Channel Control
    203
  - EMU_VMONDVDDCTRL - VMON DVDD Channel Control
    204
  - EMU_VMONIO0CTRL - VMON IOVDD0 Channel Control
    205
- 10 CMU - Clock Management Unit
  
  206
- 11 RTCC - Real Time Counter and Calendar
  
  291
  - Introduction
    291
  - Features
    292
  - Functional Description
    292
  - Counter
    293
  - Normal Mode
    294
  - Calendar Mode
    295
  - RTCC Initialization
    295
  - Capture/Compare Channels
    296
  - Interrupts and PRS Output
    298
  - Main Counter Tick PRS Output
    299
  - Energy Mode Availability
    299
  - Register Lock
    299
  - Oscillator Failure Detection
    299
  - Retention Registers
    299
  - Frame Controller Interface
    299
  - Debug Session
    299
  - Register Map
    300
  - Register Description
    301
  - RTCC_CTRL - Control Register (Async Reg)
    301
  - RTCC_PRECNT - Pre-Counter Value Register (Async Reg)
    303
  - RTCC_CNT - Counter Value Register (Async Reg)
    304
  - RTCC_COMBCNT - Combined Pre-Counter and Counter Value Register
    304
  - RTCC_TIME - Time of Day Register (Async Reg)
    305
  - RTCC_DATE - Date Register (Async Reg)
    306
  - RTCC_IF - RTCC Interrupt Flags
    307
  - RTCC_IFS - Interrupt Flag Set Register
    308
  - RTCC_IFC - Interrupt Flag Clear Register
    309
  - RTCC_IEN - Interrupt Enable Register
    311
  - RTCC_STATUS - Status Register
    312
  - RTCC_CMD - Command Register
    312
  - RTCC_SYNCBUSY - Synchronization Busy Register
    312
  - RTCC_POWERDOWN - Retention RAM Power-Down Register (Async Reg)
    313
  - RTCC_LOCK - Configuration Lock Register (Async Reg)
    313
  - RTCC_EM4WUEN - Wake up Enable
    314
  - Rtcc_Ccx_Ctrl - CC Channel Control Register (Async Reg)
    315
  - Rtcc_Ccx_Ccv - Capture/Compare Value Register (Async Reg)
    317
  - Rtcc_Ccx_Time - Capture/Compare Time Register (Async Reg)
    318
  - Rtcc_Ccx_Date - Capture/Compare Date Register (Async Reg)
    319
  - Rtcc_Retx_Reg - Retention Register
    319
- 12 WDOG - Watchdog Timer
  
  320
  - Introduction
    320
  - Features
    320
  - Functional Description
    320
  - Clock Source
    321
  - Debug Functionality
    321
  - Energy Mode Handling
    321
  - Register Access
    321
  - Warning Interrupt
    321
  - Window Interrupt
    322
  - PRS as Watchdog Clear
    323
  - PRS Rising Edge Monitoring
    323
  - Register Map
    324
  - Register Description
    325
  - WDOG_CTRL - Control Register (Async Reg)
    325
  - WDOG_CMD - Command Register (Async Reg)
    329
  - WDOG_SYNCBUSY - Synchronization Busy Register
    329
  - Wdogn_Pchx_Prsctrl - PRS Control Register (Async Reg)
    330
  - WDOG_IF - Watchdog Interrupt Flags
    331
  - WDOG_IFS - Interrupt Flag Set Register
    332
  - WDOG_IFC - Interrupt Flag Clear Register
    333
  - WDOG_IEN - Interrupt Enable Register
    334
- 13 PRS - Peripheral Reflex System
  
  335
  - Introduction
    335
  - Features
    335
  - Functional Description
    336
  - Channel Functions
    336
  - Asynchronous Mode
    336
  - Edge Detection and Clock Domains
    337
  - Configurable PRS Logic
    337
  - Producers
    337
  - Consumers
    338
  - Event on PRS
    338
  - DMA Request on PRS
    339
  - Example
    339
  - Register Map
    340
  - Register Description
    341
  - PRS_SWPULSE - Software Pulse Register
    341
  - PRS_SWLEVEL - Software Level Register
    342
  - PRS_ROUTEPEN - I/O Routing Pin Enable Register
    343
  - PRS_ROUTELOC0 - I/O Routing Location Register
    344
  - PRS_ROUTELOC1 - I/O Routing Location Register
    347
  - PRS_ROUTELOC2 - I/O Routing Location Register
    350
  - PRS_CTRL - Control Register
    353
  - PRS_DMAREQ0 - DMA Request 0 Register
    354
  - PRS_DMAREQ1 - DMA Request 1 Register
    355
  - PRS_PEEK - PRS Channel Values
    356
  - Prs_Chx_Ctrl - Channel Control Register
    357
- 14 PCNT - Pulse Counter
  
  362
  - Introduction
    362
  - Features
    362
  - Functional Description
    363
  - Pulse Counter Modes
    363
  - Single Input Oversampling Mode
    363
  - Externally Clocked Single Input Counter Mode
    363
  - Quadrature Decoder Modes
    364
  - Externally Clocked Quadrature Decoder Mode
    365
  - Oversampling Quadrature Decoder Mode
    367
  - Hysteresis
    370
  - Auxiliary Counter
    371
  - Triggered Compare and Clear
    372
  - Register Access
    373
  - Clock Sources
    373
  - Input Filter
    373
  - Edge Polarity
    374
  - PRS and Pcntn_S0In,Pcntn_S1In Inputs
    374
  - Interrupts
    374
  - Underflow and Overflow Interrupts
    374
  - Direction Change Interrupt
    375
  - Cascading Pulse Counters
    376
  - Register Map
    377
  - Register Description
    378
  - Pcntn_Ctrl - Control Register (Async Reg)
    378
  - Pcntn_Cmd - Command Register (Async Reg)
    382
  - Pcntn_Status - Status Register
    382
  - Pcntn_Cnt - Counter Value Register
    383
  - Pcntn_Top - Top Value Register
    383
  - Pcntn_Topb - Top Value Buffer Register (Async Reg)
    384
  - Pcntn_If - Interrupt Flag Register
    384
  - Pcntn_Ifs - Interrupt Flag Set Register
    385
  - Pcntn_Ifc - Interrupt Flag Clear Register
    386
  - Pcntn_Ien - Interrupt Enable Register
    387
  - Pcntn_Routeloc0 - I/O Routing Location Register
    388
  - Pcntn_Freeze - Freeze Register
    391
  - Pcntn_Syncbusy - Synchronization Busy Register
    391
  - Pcntn_Auxcnt - Auxiliary Counter Value Register
    392
  - Pcntn_Input - PCNT Input Register
    393
  - Pcntn_Ovscfg - Oversampling Config Register (Async Reg)
    395
- 15 I2C - Inter-Integrated Circuit Interface
  
  396
  - Introduction
    396
  - Features
    396
  - Functional Description
    397
  - I2C-Bus Overview
    398
  - START and STOP Conditions
    399
  - Bus Transfer
    400
  - Addresses
    401
  - 10-Bit Addressing
    401
  - Arbitration, Clock Synchronization, Clock Stretching
    402
  - Enable and Reset
    402
  - Safely Disabling and Changing Slave Configuration
    402
  - Clock Generation
    402
  - Arbitration
    403
  - Buffers
    403
  - Transmit Buffer and Shift Register
    403
  - Receive Buffer and Shift Register
    404
  - Master Operation
    405
  - Master State Machine
    406
  - Interactions
    407
  - Automatic ACK Interaction
    408
  - Reset State
    408
  - Master Transmitter
    409
  - Master Receiver
    411
  - Bus States
    413
  - Slave Operation
    413
  - Slave State Machine
    414
  - Address Recognition
    414
  - Slave Transmitter
    415
  - Slave Receiver
    417
  - Transfer Automation
    417
  - Dma
    418
  - Automatic ACK
    418
  - Automatic STOP
    418
  - Using 10-Bit Addresses
    418
  - Error Handling
    418
  - ABORT Command
    418
  - Bus Reset
    418
  - I2C-Bus Errors
    419
  - Bus Lockup
    419
  - Bus Idle Timeout
    419
  - Clock Low Timeout
    419
  - Clock Low Error
    420
  - DMA Support
    420
  - Interrupts
    420
  - Wake-Up
    420
  - Register Map
    421
  - Register Description
    422
  - I2Cn_Ctrl - Control Register
    422
  - I2Cn_Cmd - Command Register
    426
  - I2Cn_State - State Register
    427
  - I2Cn_Status - Status Register
    428
  - I2Cn_Clkdiv - Clock Division Register
    429
  - I2Cn_Saddr - Slave Address Register
    429
  - I2Cn_Saddrmask - Slave Address Mask Register
    430
  - I2Cn_Rxdata - Receive Buffer Data Register (Actionable Reads)
    430
  - I2Cn_Rxdouble - Receive Buffer Double Data Register (Actionable Reads)
    431
  - I2Cn_Rxdatap - Receive Buffer Data Peek Register
    431
  - I2Cn_Rxdoublep - Receive Buffer Double Data Peek Register
    432
  - I2Cn_Txdata - Transmit Buffer Data Register
    432
  - I2Cn_Txdouble - Transmit Buffer Double Data Register
    433
  - I2Cn_If - Interrupt Flag Register
    434
  - I2Cn_Ifs - Interrupt Flag Set Register
    437
  - I2Cn_Ifc - Interrupt Flag Clear Register
    439
  - I2Cn_Ien - Interrupt Enable Register
    442
  - I2Cn_Routepen - I/O Routing Pin Enable Register
    444
  - I2Cn_Routeloc0 - I/O Routing Location Register
    445
- 16 USART - Universal Synchronous Asynchronous Receiver/Transmitter
  
  448
  - Introduction
    448
  - Features
    449
  - Functional Description
    450
  - Modes of Operation
    451
  - Asynchronous Operation
    451
  - Frame Format
    452
  - Parity Bit Calculation and Handling
    453
  - Clock Generation
    454
  - Auto Baud Detection
    455
  - Data Transmission
    455
  - Transmit Buffer Operation
    456
  - Frame Transmission Control
    457
  - Data Reception
    457
  - Receive Buffer Operation
    458
  - Blocking Incoming Data
    459
  - Clock Recovery and Filtering
    460
  - Parity Error
    461
  - Framing Error and Break Detection
    461
  - Local Loopback
    462
  - Asynchronous Half Duplex Communication
    462
  - Single Data-Link
    462
  - Single Data-Link with External Driver
    463
  - Two Data-Links
    463
  - Large Frames
    464
  - Multi-Processor Mode
    466
  - Collision Detection
    466
  - Smartcard Mode
    467
  - Synchronous Operation
    468
  - Frame Format
    468
  - Clock Generation
    469
  - Master Mode
    470
  - Operation of Usn_Cs Pin
    470
  - Autotx
    470
  - Slave Mode
    471
  - Synchronous Half Duplex Communication
    471
  - I2S
    471
  - Word Format
    471
  - Major Modes
    472
  - Using I2S Mode
    474
  - Hardware Flow Control
    474
  - Debug Halt
    474
  - PRS-Triggered Transmissions
    474
  - PRS RX Input
    474
  - PRS CLK Input
    475
  - DMA Support
    475
  - Timer
    476
  - Response Timeout
    478
  - RX Timeout
    479
  - Break Detect
    479
  - TX Start Delay
    480
  - Inter-Character Space
    480
  - TX Chip Select End Delay
    480
  - Response Delay
    480
  - Combined TX and RX Example
    481
  - Combined TX Delay and RX Break Detect
    481
  - Other Stop Conditions
    481
  - Interrupts
    481
  - Irda Modulator/ Demodulator
    482
  - Register Map
    483
  - Register Description
    484
  - Usartn_Ctrl - Control Register
    484
  - Usartn_Frame - USART Frame Format Register
    489
  - Usartn_Trigctrl - USART Trigger Control Register
    492
  - Usartn_Cmd - Command Register
    495
  - Usartn_Status - USART Status Register
    496
  - Usartn_Clkdiv - Clock Control Register
    498
  - Usartn_Rxdatax - RX Buffer Data Extended Register (Actionable Reads)
    499
  - Usartn_Rxdata - RX Buffer Data Register (Actionable Reads)
    499
  - Usartn_Rxdoublex - RX Buffer Double Data Extended Register (Actionable Reads)
    500
  - Usartn_Rxdouble - RX FIFO Double Data Register (Actionable Reads)
    501
  - Usartn_Rxdataxp - RX Buffer Data Extended Peek Register
    501
  - Usartn_Rxdoublexp - RX Buffer Double Data Extended Peek Register
    502
  - Usartn_Txdatax - TX Buffer Data Extended Register
    503
  - Usartn_Txdata - TX Buffer Data Register
    504
  - Usartn_Txdoublex - TX Buffer Double Data Extended Register
    505
  - Usartn_Txdouble - TX Buffer Double Data Register
    506
  - Usartn_If - Interrupt Flag Register
    507
  - Usartn_Ifs - Interrupt Flag Set Register
    509
  - Usartn_Ifc - Interrupt Flag Clear Register
    511
  - Usartn_Ien - Interrupt Enable Register
    514
  - Usartn_Irctrl - Irda Control Register
    516
  - Usartn_Input - USART Input Register
    518
  - Usartn_I2Sctrl - I2S Control Register
    521
  - Usartn_Timing - Timing Register
    522
  - Usartn_Ctrlx - Control Register Extended
    525
  - Usartn_Timecmp0 - Used to Generate Interrupts and Various Delays
    526
  - Usartn_Timecmp1 - Used to Generate Interrupts and Various Delays
    528
  - Usartn_Timecmp2 - Used to Generate Interrupts and Various Delays
    530
  - Usartn_Routepen - I/O Routing Pin Enable Register
    532
  - Usartn_Routeloc0 - I/O Routing Location Register
    534
  - Usartn_Routeloc1 - I/O Routing Location Register
    539
- 17 LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
  
  542
  - Introduction
    542
  - Features
    543
  - Functional Description
    544
  - Frame Format
    545
  - Parity Bit Calculation and Handling
    545
  - Clock Source
    545
  - Clock Generation
    546
  - Data Transmission
    546
  - Transmit Buffer Operation
    547
  - Frame Transmission Control
    547
  - Data Reception
    548
  - Receive Buffer Operation
    548
  - Blocking Incoming Data
    549
  - Data Sampling
    549
  - Parity Error
    549
  - Framing Error and Break Detection
    550
  - Programmable Start Frame
    550
  - Programmable Signal Frame
    550
  - Multi-Processor Mode
    551
  - Loopback
    551
  - Half Duplex Communication
    551
  - Single Data-Link
    552
  - Single Data-Link with External Driver
    552
  - Two Data-Links
    552
  - Transmission Delay
    552
  - PRS RX Input
    553
  - DMA Support
    553
  - Pulse Generator/ Pulse Extender
    554
  - Interrupts
    554
  - Register Access
    554
  - Register Map
    555
  - Register Description
    556
  - Leuartn_Ctrl - Control Register (Async Reg)
    556
  - Leuartn_Cmd - Command Register (Async Reg)
    560
  - Leuartn_Status - Status Register
    561
  - Leuartn_Clkdiv - Clock Control Register (Async Reg)
    562
  - Leuartn_Startframe - Start Frame Register (Async Reg)
    562
  - Leuartn_Sigframe - Signal Frame Register (Async Reg)
    563
  - Leuartn_Rxdatax - Receive Buffer Data Extended Register (Actionable Reads)
    563
  - Leuartn_Rxdata - Receive Buffer Data Register (Actionable Reads)
    564
  - Leuartn_Rxdataxp - Receive Buffer Data Extended Peek Register
    564
  - Leuartn_Txdatax - Transmit Buffer Data Extended Register (Async Reg)
    565
  - Leuartn_Txdata - Transmit Buffer Data Register (Async Reg)
    566
  - Leuartn_If - Interrupt Flag Register
    567
  - Leuartn_Ifs - Interrupt Flag Set Register
    568
  - Leuartn_Ifc - Interrupt Flag Clear Register
    569
  - Leuartn_Ien - Interrupt Enable Register
    570
  - Leuartn_Pulsectrl - Pulse Control Register (Async Reg)
    571
  - Leuartn_Freeze - Freeze Register
    572
  - Leuartn_Syncbusy - Synchronization Busy Register
    573
  - Leuartn_Routepen - I/O Routing Pin Enable Register
    574
  - Leuartn_Routeloc0 - I/O Routing Location Register
    575
  - Leuartn_Input - LEUART Input Register
    578
- 18 TIMER - Timer/Counter
  
  579
  - Introduction
    579
  - Features
    580
  - Functional Description
    581
  - Counter Modes
    581
  - Events
    582
  - Operation
    582
  - Clock Source
    583
  - Peripheral Clock (HFPERCLK)
    583
  - Compare/ Capture Channel 1 Input
    583
  - Underflow/Overflow from Neighboring Timer
    583
  - One-Shot Mode
    583
  - Top Value Buffer
    584
  - Quadrature Decoder
    585
  - X2 Decoding Mode
    586
  - X4 Decoding Mode
    586
  - TIMER Rotational Position
    587
  - Compare/Capture Channels
    587
  - Input Pin Logic
    587
  - Compare/Capture Registers
    587
  - Input Capture
    588
  - Period/Pulse-Width Capture
    589
  - Compare
    590
  - Compare Mode Registers
    591
  - Frequency Generation (FRG)
    592
  - Pulse-Width Modulation (PWM)
    592
  - Up-Count (Single-Slope) PWM
    593
  - Count Mode
    594
  - Up/Down-Count (Dual-Slope) PWM
    595
  - Count Mode
    596
  - Timer Configuration Lock
    596
  - Dead-Time Insertion Unit (TIMER0 Only)
    597
  - Output Polarity
    600
  - PRS Channel as a Source
    601
  - Fault Handling
    601
  - Action on Fault
    601
  - Exiting Fault State
    601
  - DTI Configuration Lock
    601
  - Debug Mode
    601
  - Interrupts, DMA and PRS Output
    602
  - GPIO Input/Output
    602
  - Register Map
    603
  - Register Description
    604
  - Timern_Ctrl - Control Register
    604
  - Timern_Cmd - Command Register
    607
  - Timern_Status - Status Register
    608
  - Timern_If - Interrupt Flag Register
    612
  - Timern_Ifs - Interrupt Flag Set Register
    613
  - Timern_Ifc - Interrupt Flag Clear Register
    614
  - Timern_Ien - Interrupt Enable Register
    616
  - Timern_Top - Counter Top Value Register
    617
  - Timern_Topb - Counter Top Value Buffer Register
    617
  - Timern_Cnt - Counter Value Register
    618
  - Timern_Lock - TIMER Configuration Lock Register
    618
  - Timern_Routepen - I/O Routing Pin Enable Register
    619
  - Timern_Routeloc0 - I/O Routing Location Register
    620
  - Timern_Routeloc2 - I/O Routing Location Register
    625
  - Timern_Ccx_Ctrl - CC Channel Control Register
    629
  - Timern_Ccx_Ccv - CC Channel Value Register (Actionable Reads)
    632
  - Timern_Ccx_Ccvp - CC Channel Value Peek Register
    633
  - Timern_Ccx_Ccvb - CC Channel Buffer Register
    633
  - Timern_Dtctrl - DTI Control Register
    634
  - Timern_Dttime - DTI Time Control Register
    637
  - Timern_Dtfc - DTI Fault Configuration Register
    638
  - Timern_Dtogen - DTI Output Generation Enable Register
    641
  - Timern_Dtfault - DTI Fault Register
    642
  - Timern_Dtfaultc - DTI Fault Clear Register
    643
  - Timern_Dtlock - DTI Configuration Lock Register
    644
- 19 LETIMER - Low Energy Timer
  
  645
  - Introduction
    645
  - Features
    645
  - Functional Description
    646
  - Timer
    646
  - Compare Registers
    646
  - Top Value
    647
  - Buffered Top Value
    647
  - Repeat Modes
    647
  - Free-Running Mode
    648
  - One-Shot Mode
    649
  - Buffered Mode
    650
  - Double Mode
    651
  - Clock Source
    651
  - PRS Input Triggers
    652
  - Debug
    652
  - Underflow Output Action
    653
  - PRS Output
    655
  - Examples
    655
  - Triggered Output Generation
    656
  - Continuous Output Generation
    657
  - PWM Output
    658
  - Interrupts
    658
  - Register Access
    659
  - Register Map
    659
  - Register Description
    660
  - Letimern_Ctrl - Control Register (Async Reg)
    660
  - Letimern_Cmd - Command Register
    662
  - Letimern_Status - Status Register
    663
  - Letimern_Cnt - Counter Value Register
    663
  - Letimern_Comp0 - Compare Value Register 0 (Async Reg)
    664
  - Letimern_Comp1 - Compare Value Register 1 (Async Reg)
    664
  - Letimern_Rep0 - Repeat Counter Register 0 (Async Reg)
    665
  - Letimern_Rep1 - Repeat Counter Register 1 (Async Reg)
    665
  - Letimern_If - Interrupt Flag Register
    666
  - Letimern_Ifs - Interrupt Flag Set Register
    667
  - Letimern_Ifc - Interrupt Flag Clear Register
    668
  - Letimern_Ien - Interrupt Enable Register
    669
  - Letimern_Syncbusy - Synchronization Busy Register
    669
  - Letimern_Routepen - I/O Routing Pin Enable Register
    670
  - Letimern_Routeloc0 - I/O Routing Location Register
    671
  - Letimern_Prssel - PRS Input Select Register
    674
- 20 CRYOTIMER - Ultra Low Energy Timer/Counter
  
  678
  - Introduction
    678
  - Features
    678
  - Functional Description
    678
  - Block Diagram
    679
  - Operation
    680
  - Debug Mode
    680
  - Energy Mode Availability
    680
  - Register Map
    681
  - Register Description
    682
  - CRYOTIMER_CTRL - Control Register
    682
  - CRYOTIMER_PERIODSEL - Interrupt Duration
    683
  - CRYOTIMER_CNT - Counter Value
    685
  - CRYOTIMER_EM4WUEN - Wake up Enable
    685
  - CRYOTIMER_IF - Interrupt Flag Register
    686
  - CRYOTIMER_IFS - Interrupt Flag Set Register
    686
  - CRYOTIMER_IFC - Interrupt Flag Clear Register
    687
  - CRYOTIMER_IEN - Interrupt Enable Register
    687
- 21 ACMP - Analog Comparator
  
  688
  - Introduction
    688
  - Features
    688
  - Functional Description
    689
  - Warm-Up Time
    690
  - Response Time
    690
  - Hysteresis
    691
  - Input Selection
    692
  - Capacitive Sense Mode
    694
  - Interrupts and PRS Output
    695
  - Output to GPIO
    696
  - APORT Conflicts
    696
  - Supply Voltage Monitoring
    696
  - Register Map
    696
  - Register Description
    697
  - Acmpn_Ctrl - Control Register
    697
  - Acmpn_Inputsel - Input Selection Register
    701
  - Acmpn_Status - Status Register
    706
  - Acmpn_If - Interrupt Flag Register
    707
  - Acmpn_Ifs - Interrupt Flag Set Register
    707
  - Acmpn_Ifc - Interrupt Flag Clear Register
    708
  - Acmpn_Ien - Interrupt Enable Register
    709
  - Acmpn_Aportreq - APORT Request Status Register
    710
  - Acmpn_Aportconflict - APORT Conflict Status Register
    711
  - Acmpn_Hysteresis0 - Hysteresis 0 Register
    713
  - Acmpn_Hysteresis1 - Hysteresis 1 Register
    714
  - Acmpn_Routepen - I/O Routing Pine Enable Register
    715
  - Acmpn_Routeloc0 - I/O Routing Location Register
    716
- 22 ADC - Analog to Digital Converter
  
  718
  - Introduction
    718
  - Features
    719
  - Functional Description
    720
  - Clock Selection
    721
  - Conversions
    721
  - ADC Modes
    722
  - Single Channel Mode
    722
  - Scan Mode
    722
  - Warm-Up Time
    723
  - Input Selection
    725
  - Configuring ADC Inputs in Single Channel Mode
    727
  - Configuring ADC Inputs in Scan Mode
    728
  - APORT Conflicts
    730
  - Reference Selection and Input Range Definition
    730
  - Basic Full-Scale Voltage Configuration
    730
  - Advanced Full-Scale Voltage Configuration
    731
  - Programming of Bias Current
    732
  - Feature Set
    732
  - Conversion Tailgating
    733
  - Repetitive Mode
    733
  - Conversion Trigger
    734
  - Output Results
    735
  - Resolution
    736
  - Oversampling
    736
  - Adjustment
    737
  - Channel Connection
    737
  - Temperature Measurement
    737
  - ADC as a Random Number Generator
    738
  - Interrupts, PRS Output
    738
  - DMA Request
    738
  - Calibration
    738
  - Offset Calibration
    739
  - Gain Calibration
    739
  - EM2 or EM3 Operation
    740
  - ASYNC ADC_CLK Usage Restrictions and Benefits
    740
  - Window Compare Function
    740
  - ADC Programming Model
    741
  - Register Map
    742
  - Register Description
    743
  - Adcn_Ctrl - Control Register
    743
  - Adcn_Cmd - Command Register
    746
  - Adcn_Status - Status Register
    747
  - Adcn_Singlectrl - Single Channel Control Register
    748
  - Adcn_Singlectrlx - Single Channel Control Register Continued
    753
  - Adcn_Scanctrl - Scan Control Register
    756
  - Adcn_Scanctrlx - Scan Control Register Continued
    759
  - Adcn_Scanmask - Scan Sequence Input Mask Register
    762
  - Adcn_Scaninputsel - Input Selection Register for Scan Mode
    765
  - Adcn_Scannegsel - Negative Input Select Register for Scan
    768
  - Adcn_Cmpthr - Compare Threshold Register
    771
  - Adcn_Biasprog - Bias Programming Register for Various Analog Blocks Used in ADC Operation
    772
  - Adcn_Cal - Calibration Register
    773
  - Adcn_If - Interrupt Flag Register
    775
  - Adcn_Ifs - Interrupt Flag Set Register
    777
  - Adcn_Ifc - Interrupt Flag Clear Register
    778
  - Adcn_Ien - Interrupt Enable Register
    779
  - Adcn_Singledata - Single Conversion Result Data (Actionable Reads)
    780
  - Adcn_Scandata - Scan Conversion Result Data (Actionable Reads)
    780
  - Adcn_Singledatap - Single Conversion Result Data Peek Register
    781
  - Adcn_Scandatap - Scan Sequence Result Data Peek Register
    781
  - Adcn_Scandatax - Scan Sequence Result Data + Data Source Register (Actionable Reads)
    782
  - Adcn_Scandataxp - Scan Sequence Result Data + Data Source Peek Register
    782
  - Adcn_Aportreq - APORT Request Status Register
    783
  - Adcn_Aportconflict - APORT Conflict Status Register
    784
  - Adcn_Singlefifocount - Single FIFO Count Register
    786
  - Adcn_Scanfifocount - Scan FIFO Count Register
    786
  - Adcn_Singlefifoclear - Single FIFO Clear Register
    787
  - Adcn_Scanfifoclear - Scan FIFO Clear Register
    787
  - Adcn_Aportmasterdis - APORT Bus Master Disable Register
    788
- 23 IDAC - Current Digital to Analog Converter
  
  791
  - Introduction
    791
  - Features
    791
  - Functional Description
    792
  - Current Programming
    792
  - IDAC Enable and Warm-Up
    792
  - Output Control
    793
  - Output Modes
    793
  - APORT Configuration
    794
  - Interrupts
    795
  - Minimizing Output Transition
    795
  - Duty Cycle Configuration
    795
  - Calibration
    795
  - PRS Input
    795
  - PRS Triggered Charge Injection
    796
  - Register Map
    796
  - Register Description
    797
  - IDAC_CTRL - Control Register
    797
  - IDAC_CURPROG - Current Programming Register
    800
  - IDAC_DUTYCONFIG - Duty Cycle Configauration Register
    801
  - IDAC_STATUS - Status Register
    801
  - IDAC_IF - Interrupt Flag Register
    802
  - IDAC_IFS - Interrupt Flag Set Register
    802
  - IDAC_IFC - Interrupt Flag Clear Register
    803
  - IDAC_IEN - Interrupt Enable Register
    803
  - IDAC_APORTREQ - APORT Request Status Register
    804
  - IDAC_APORTCONFLICT - APORT Request Status Register
    804
- 24 GPCRC - General Purpose Cyclic Redundancy Check
  
  805
  - Introduction
    805
  - Features
    805
  - Functional Description
    806
  - Polynomial Specification
    807
  - Input and Output Specification
    807
  - Automatic Initialization
    807
  - DMA Usage
    807
  - Byte-Level Bit Reversal and Byte Reordering
    808
  - Register Map
    810
  - Register Description
    811
  - GPCRC_CTRL - Control Register
    811
  - GPCRC_CMD - Command Register
    813
  - GPCRC_INIT - CRC Init Value
    813
  - GPCRC_POLY - CRC Polynomial Value
    814
  - GPCRC_INPUTDATA - Input 32-Bit Data Register
    814
  - GPCRC_INPUTDATAHWORD - Input 16-Bit Data Register
    815
  - GPCRC_INPUTDATABYTE - Input 8-Bit Data Register
    815
  - GPCRC_DATA - CRC Data Register
    816
  - GPCRC_DATAREV - CRC Data Reverse Register
    816
  - GPCRC_DATABYTEREV - CRC Data Byte Reverse Register
    817
- 25 CRYPTO - Crypto Accelerator
  
  818
- 26 GPIO - General Purpose Input/Output
  
  873
  - Introduction
    873
  - Features
    874
  - Functional Description
    875
  - Pin Configuration
    876
  - Over Voltage Tolerance
    878
  - Alternate Port Control
    878
  - Drive Strength
    878
  - Slewrate
    878
  - Input Disable
    878
  - Configuration Lock
    878
  - EM4 Wake-Up
    879
  - EM4 Retention
    879
  - Alternate Functions
    880
  - Analog Connections
    880
  - Debug Connections
    880
  - Interrupt Generation
    880
  - Edge Interrupt Generation
    881
  - Level Interrupt Generation
    882
  - Output to PRS
    882
  - Synchronization
    882
  - Register Map
    883
  - Register Description
    885
  - Gpio_Px_Ctrl - Port Control Register
    885
  - Gpio_Px_Model - Port Pin Mode Low Register
    887
  - Gpio_Px_Modeh - Port Pin Mode High Register
    893
  - Gpio_Px_Dout - Port Data out Register
    898
  - Gpio_Px_Douttgl - Port Data out Toggle Register
    899
  - Gpio_Px_Din - Port Data in Register
    899
  - Gpio_Px_Pinlockn - Port Unlocked Pins Register
    900
  - Gpio_Px_Ovtdis - over Voltage Disable for All Modes
    900
  - GPIO_EXTIPSELL - External Interrupt Port Select Low Register
    901
  - GPIO_EXTIPSELH - External Interrupt Port Select High Register
    904
  - GPIO_EXTIPINSELL - External Interrupt Pin Select Low Register
    907
  - GPIO_EXTIPINSELH - External Interrupt Pin Select High Register
    910
  - GPIO_EXTIRISE - External Interrupt Rising Edge Trigger Register
    913
  - GPIO_EXTIFALL - External Interrupt Falling Edge Trigger Register
    913
  - GPIO_EXTILEVEL - External Interrupt Level Register
    914
  - GPIO_IF - Interrupt Flag Register
    915
  - GPIO_IFS - Interrupt Flag Set Register
    915
  - GPIO_IFC - Interrupt Flag Clear Register
    916
  - GPIO_IEN - Interrupt Enable Register
    916
  - GPIO_EM4WUEN - EM4 Wake up Enable Register
    917
  - GPIO_ROUTEPEN - I/O Routing Pin Enable Register
    918
  - GPIO_ROUTELOC0 - I/O Routing Location Register
    919
  - GPIO_INSENSE - Input Sense Register
    919
  - GPIO_LOCK - Configuration Lock Register
    920
- 27 APORT - Analog Port
  
  921
  - Introduction
    921
  - Features
    921
  - Functional Description
    922
  - APORT ABUS Naming
    923
  - Managing Abuses
    925
- Appendix 1. Abbreviations
  
  927
Gpio - General Purpose Input/Output/

951

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Motherboard Microcontrollers Computer Hardware Control Unit Adapter

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Silicon Laboratories EFM32JG1 Manuals

Silicon Laboratories EFM32JG1 Reference Manual (953 pages)

Table of Contents

Table of Contents

1 About this Document

2 System Overview

3 System Processor

4 Memory and Bus System

5 DBG - Debug Interface

6 MSC - Memory System Controller

7 LDMA - Linked DMA Controller

8 RMU - Reset Management Unit

9 EMU - Energy Management Unit

10 CMU - Clock Management Unit

11 RTCC - Real Time Counter and Calendar

12 WDOG - Watchdog Timer

13 PRS - Peripheral Reflex System

14 PCNT - Pulse Counter

15 I2C - Inter-Integrated Circuit Interface

16 USART - Universal Synchronous Asynchronous Receiver/Transmitter

17 LEUART - Low Energy Universal Asynchronous Receiver/Transmitter

18 TIMER - Timer/Counter

19 LETIMER - Low Energy Timer

20 CRYOTIMER - Ultra Low Energy Timer/Counter

21 ACMP - Analog Comparator

22 ADC - Analog to Digital Converter

23 IDAC - Current Digital to Analog Converter

24 GPCRC - General Purpose Cyclic Redundancy Check

25 CRYPTO - Crypto Accelerator

26 GPIO - General Purpose Input/Output

27 APORT - Analog Port

Appendix 1. Abbreviations

Gpio - General Purpose Input/Output/

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