Register Descriptions; Figure 12.15. Sp: Stack Pointer; Figure 12.16. Dpl: Data Pointer Low Byte; Figure 12.17. Dph: Data Pointer High Byte - Silicon Laboratories C8051F120 Manual

12.6.4. Register Descriptions

Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not
be set to logic l. Future product versions may use these bits to implement new features in which case the reset value
of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included
in the sections of the datasheet associated with their corresponding system function.
R/W R/W
Bit7 Bit6
Bits7-0: SP: Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before
every PUSH operation. The SP register defaults to 0x07 after reset.
R/W R/W
Bit7 Bit6
Bits7-0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed
XRAM and FLASH memory.
R/W R/W
Bit7 Bit6
Bits7-0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed
XRAM and FLASH memory.

Figure 12.15. SP: Stack Pointer

R/W R/W R/W
Bit5 Bit4 Bit3

Figure 12.16. DPL: Data Pointer Low Byte

R/W R/W R/W
Bit5 Bit4 Bit3

Figure 12.17. DPH: Data Pointer High Byte

R/W R/W R/W
Bit5 Bit4 Bit3
C8051F120/1/2/3/4/5/6/7
R/W R/W
Bit2 Bit1
R/W R/W
Bit2 Bit1
R/W R/W
Bit2 Bit1
Rev. 1.2
R/W Reset Value
00000111
Bit0
SFR Address: 0x81
SFR Page: All Pages
R/W Reset Value
00000000
Bit0
SFR Address: 0x82
SFR Page: All Pages
R/W Reset Value
00000000
Bit0
SFR Address: 0x83
SFR Page: All Pages
143