Oscillation Stabilization Wait Time; Operation - Panasonic F77G User Manual

Sequence at Reset
(1) When reset pin comes to high level from low level, the innternal 14-bit counter (It can be used as
watchdog timer, too.) starts its operation by system clock. The period from starting its count from
its overflow is called oscillation stabilization wait time.
(2) During reset, internal register and special function register are initiated.
(3) After oscillation stabilization wait time, internal reset is released and program is started
from the address written at address X '4000' at interrupt rector table.
VDD
NRST
OSC2/XO
internal RST
Oscillation stabilization
wait time
Figure 2-8-2 Reset Released Sequence
Chapter 2 CPU Basics
II - 39
Reset