Sun Microsystems UltraSPARC-I User Manual page 97

raSPARC User's Manual
CLK
0
CYCLE
TSYN_WR_L
TOE_L
ECAT
TDATA
DSYN_WR_L
DOE_L
ECAD
EDATA
Figure 7-7 Timing for Coherent Writes with E-to-M State Transition (1–1–1 Mode)
Otherwise, the tag port is available for a tag check of a younger store during the
data write. In the timing diagram shown in Figure 7-5 on page 81, the store buffer
is empty when the first write request is made, which is why there is no overlap
between the tag accesses and the write accesses. In normal operation, if the line is
in M state, the tag access for one write can be done in parallel with the data write
of previous write (E state updates cannot be overlapped). This independence of
the tag and data buses make the peak store bandwidth as high as the load band-
width (one per cycle). Figure 7-8 shows the 1–1–1 Mode overlap of tag and data
accesses. The data for three previous writes (W0, W1 and W2) is written while
three tag accesses (reads) are made for three younger stores (R3, R4 and R5).
CLK
CYCLE
0
SYN_WR_L
TOE_L
ECAT
TDATA
SYN_WR_L
DOE_L
ECAD
EDATA
Figure 7-8 Timing Overlap: Tag Access / Data Write for Coherent Writes (1–1–1 Mode)
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If the line is in Shared (S) or Owned (O) state, a read for ownership is performed
1 2 3
R0 R1 R2
R0 R1 R2
A0_tag A1_tag A2_tag
D0_tag
1 2 3
R3 R4 R5
R3 R4 R5
A3_tag A4_tag A5_tag
W0 W1 W2
W0 W1 W2
A0_data A1_data A2_data
D0_data D1_data
4 5 6
U0
U0
A0_tag A1_tag
D1_tag D2_tag D0_tag
W0
W0
A0_data A1_data A2_data
D0_data D1_data D2_data
4 5
D3_tag D4_tag
D2_data
7 8 9
U1 U2
U1 U2
A2_tag
D1_tag D2_tag
W1 W2
W1 W2
6 7
D5_tag