Sun Microsystems UltraSPARC-I User Manual page 138

7.13.3 P_REPLY and S_REPLY Timing
The following figures show the data flow on SYSDATA due to S_REPLY and
P_REPLY with no data stalls. Figure 7-25 also shows the timing of the
interconnect_ECC_Valid signal with respect to the S_REPLY. Section 7.13.4 dis-
cusses data flow timing with data stalls.
S_REPLY
Data on Bus
Figure 7-24
interconnect_ECC_Valid
Data on Bus
S_REPLY to Data Sink
Figure 7-25
S_REPLY to Data Source
Data on Bus
S_REPLY to Data Sink
P_REPLY from Slave
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S_WAB
2 clocks
S_REPLY Timing: UltraSPARC Sourcing Block Write—No Data Stall
S_REPLY Timing: UltraSPARC Receiving Block Write—No Data Stall
P_RAS
min 2 clocks
7. UltraSPARC External Interfaces
D[0] D[1] D[2] D[3]
D[0] D[1]
S_SWB
1 clock
S_SRS
D[0]
S_SWB
1 clock
2 clocks
D[2] D[3]
D[1] D[2] D[3]