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raSPARC User's Manual
6
3
rs1
rs2
sign-extended
8 msb
rd
Figure 13-12
FMUL8ULx16 Operation
.5.4.6 FMULD8SUx16
FMULD8SUx16 multiplies the upper 8 bits of each 16-bit signed value in rs1 by
the corresponding signed 16-bit fixed point signed integer in rs2. The 24-bit prod-
uct is shifted left by 8-bits to make up a 32-bit result. The result is stored in the
corresponding 32-bit of the destination rd register. The operation is illustrated in
Figure 13-13.
rs1
rs2
6
3
rd
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5
4
3
7
5
9
*
*
sign-extended
8 msb
4
3
0
9
00000000
2
3
1
3
1
5
*
sign-extended
sign-extended
8 msb
8 msb
2
3
1
3
1
5
*
7
0
*
7
0
*
7
0
00000000
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