Multiple Outstanding Transactions - Sun Microsystems UltraSPARC-I User Manual

raSPARC User's Manual
Data Stall
Data on Bus
S_REPLY to Data Sink
Figure 7-30 Data_Stall to
In Figure 7-30 latching of the first quadword D

14 Multiple Outstanding Transactions

14.1 Ordering of S_REPLYs
UltraSPARC-I supports only one outstanding 64-byte read (P_RD*_REQ or
P_NCBRD_REQ in Class 0). In addition, since a single read buffer is used for all
reads, UltraSPARC-I supports only one outstanding read of any type. Thus,
P_RD*_REQ or P_NCBRD_REQ in Class 0 and P_NCRD_REQ in Class 1 cannot
be outstanding simultaneously.
UltraSPARC-II supports three outstanding 64-byte reads (P_RD*_REQ or
P_NCBRD_REQ in Class 0). As in UltraSPARC-I, P_RD*_REQ / P_NCBRD_REQ
is mutually exclusive with P_NCRD_REQ. if any P_NCRD_REQ is outstanding,
UltraSPARC-II will not issue any other request. Finally, UltraSPARC-II will not is-
sue a P_NCRD_REQ if any Class 0 transaction is outstanding.
UltraSPARC issues all other transactions in Class 1, and can have many outstand-
ing. Multiple Class 1 transactions must be completed in the same order that the
address packets are issued. This presents some issues with implementing coher-
ent read / Writeback pairs in systems with another cache coherent memory re-
questor (or another UltraSPARC). The SC may need to maintain intermediate
state to track either the new read miss line or the Writeback line. The read miss
and Writeback may complete in any order, and the Writeback may be queued be-
hind other Class 1 transactions.
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64-byte reads must be completed in order. Coherent Writebacks also must be
S_REPLY
UltraSPARC
Sinking Data
D[0] D[1]
is deferred by one clock cycle.
0
D[2] D[3]