Sun Microsystems UltraSPARC-I User Manual page 304

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the W Stage . If the branch in the previous example was predicted not taken but
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actually was taken:
setcc
BPcc (mispredicted)
FADD (delay slot)
f0 (sequential)
FMUL
FMUL f0,f0,f0 (branch target)
If an annulling branch is predicted not taken, the delay slot is still dispatched.
Multicycle instructions (except load instructions) run to completion, even if the
delay slot instruction is annulled. For example:
BPcc, a (not taken)
imul
(delay slot)
The imul unit is busy for the duration of the multiply.
An annulled delay slot other than a load affects subsequent dependency checking
until the delay slot reaches the W
BPcc, a (not taken)
FDIV f0 (delay slot)
FADD f0,f0,f1 (sequential)
In the example above, the
struction completes.
A predicted annulled load does not affect dependency checking after it is dis-
patched. For example:
BPcc, a (predicted not taken)
fld
f0 (delay slot)
FADD f0,f0,f1 (sequential)
1. The W Stage is a virtual stage that is normally not visible to the programmer.
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G E C
G E C
G E C
G E C
G E C N N
1 2
G E E E
Stage. For example:
1
G E C N
1
G E C
instruction is stalled in issue until the
FADD
G E C N
1
G E C N
1
G E C
17. Grouping Rules and Stalls
N N N W
1 2 3
N N N W
1 2 3
N N N W
1 2 3
N N N W W
1 2 3 1
G
N W
3
E E E . . .
N N W
2 3
N N N W W
1 2 3 1
G
FDIV
N N W
2 3
N N W
2 3
N N N W
1 2 3
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