Sun Microsystems UltraSPARC-I User Manual page 112

Table 7-9 Transitions Allowed for Cache Coherence Protocol
Transition
I E Load miss; data coming from memory to an invalid
line (no other cache has the data).
I S Load miss; data provided by another cache or memory
to an invalid line (another cache has the data)
I-Cache miss or PREFETCH.
I M Store miss, atomic miss on invalid line, PREFETCH.
E M Store hit or atomic hit to Exclusive Clean line.
E S Request from system to share this line (load miss from
another processor).
E I i) A clean line is victimized by the processor.
I-Cache miss.
Write miss.
ii) Request from system to copyback and invalidate
this line (store miss from another processor).
iii) Request from SC to invalidate this line (block store
from another processor)
S M Store hit, atomic hit to Shared Clean line, PREFETCH.
S I i) A Shared Clean line is victimized by UltraSPARC.
I-Cache miss.
Write hit on shared line.
ii) Another processor wants to write this shared line.
iii) Request from SC to invalidate this line (block store
from another processor).
M O Request from another processor to read a modified
line, memory is not updated (as opposed to M
i) A Modified line is victimized by the processor
M, O I (Writeback).
ii) Request from system to copyback and invalidate
this line (store miss from another processor).
iii) Request from system to invalidate this line (block
store from another processor)
M, O S Request from another processor to read this line, mem-
ory is updated so line becomes clean (c.f. M
M Store hit, atomic hit to Modified line, PREFETCH.
O
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Description
S).
O)
7. UltraSPARC External Interfaces
Transaction Req
Acknowledgment
to/from Port
P_RDS_REQ S_RBU
P_RDS_REQ S_RBS
P_RDSA_REQ S_RBS
P_RDO_REQ S_RBU
No Transaction No Transaction
S_CPB_REQ, P_SACK | P_SACKD
S_CPB_MSI_REQ followed by S_CRAB
P_RDS_REQ S_RBU or S_RBS
or
P_RDSA_REQ
S_RBS
or
P_RDO_REQ
S_RBU
S_CPI_REQ P_SACK|P_SACKD
followed by S_CRAB
S_INV_REQ P_SACK|P_SACKD
P_RDO_REQ S_OAK
P_RDS_REQ S_RBU or S_RBS
or
P_RDSA_REQ S_RBS
or
P_RDO_REQ S_RBU
S_INV_REQ P_SACK|P_SACKD
or
S_CPI_REQ
P_SACK|P_SACKD
followed by S_CRAB
S_INV_REQ P_SACK|P_SACKD
S_CPB_REQ P_SACK|P_SACKD
followed by S_CRAB
P_WRB_REQ S_WAB or S_WBCAN
if system takes ownership
before completing Writeback
S_CPI_REQ P_SACK|P_SACKD
followed by S_CRAB
S_INV_REQ P_SACK|P_SACKD
S_CPB_MSI_REQ P_SACK|P_SACKD
followed by S_CRAB
P_RDO_REQ S_OAK
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