Sun Microsystems UltraSPARC-I User Manual page 81

raSPARC User's Manual
An ASI store to the TLB Data In register initiates an automatic atomic replace-
ment of the TLB Entry pointed to by the current contents of the TLB Replacement
register "Replace" field. The TLB data and tag are formed as in the case of an ASI
store to the TLB Data Access register described above.
Warning – Stores to the Data In register are not guaranteed to replace the
previous TLB entry causing a fault. In particular, to change an entry's attribute
bits, software must explicitly demap the old entry before writing the new entry;
otherwise, a multiple match error condition can result.
An ASI load from the TLB Data Access register initiates an internal read of the
data portion of the specified TLB entry.
An ASI load from the TLB Tag Read register initiates an internal read of the tag
portion of the specified TLB entry.
ASI loads from the TLB Data In register are not supported.
9.10 I-/D-MMU Demap
Demap is an MMU operation, as opposed to a register as described above. The
purpose of Demap is to remove zero, one, or more entries in the TLB. Two types
of Demap operation are provided: Demap page, and Demap context. Demap
page removes zero or one TLB entry that matches exactly the specified virtual
page number. Demap page may in fact remove more than one TLB entry in the
condition of a multiple TLB match, but this is an error condition of the TLB and
has undefined results. Demap context removes zero, one, or many TLB entries
that match the specified context identifier.
Demap is initiated by a STXA with ASI=57
D-MMU demap. It removes TLB entries from an on-chip TLB. UltraSPARC does
not support bus-based demap. Figure 6-15 shows the Demap format:
63
63
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VA<63:13>
13
—
for I-MMU demap or 5F
16
ignored Type Context
12 7 6 5
for
16
0000
Address
4 3 0
Data
0