Sun Microsystems UltraSPARC-I Manuals

Manuals and User Guides for Sun Microsystems UltraSPARC-I. We have 1 Sun Microsystems UltraSPARC-I manual available for free PDF download: User Manual

Sun Microsystems UltraSPARC-I User Manual

Sun Microsystems UltraSPARC-I User Manual (410 pages)

Brand: Sun Microsystems | Category: Computer Hardware | Size: 1.17 MB

Table of Contents
4
Section I - Introducing Ultrasparc
16
1 Ultrasparc Basics

18
- Overview
  18
- Design Philosophy
  18
- Component Overview
  20
- Preface
  
  24
  - Overview
    24
  - A Brief History of SPARC
    24
  - How to Use this Book
    25
  - Ultrasparc Subsystem
    25
2 Processor Pipeline

26
- Introductions
  26
- Pipeline Stages
  27
3 Cache Organization

32
- Introduction
  32
4 Overview of the MMU

36
- Introduction
  36
- Virtual Address Translation
  36
  - Section II - Going Deeper
    40
5 Cache and Memory Interactions ........................................................................................ Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | Www.artisantg.com

42
- Cache Flushing
  42
- Memory Accesses and Cacheability
  44
- Load Buffer
  54
- Store Buffer
  55
6 MMU Internal Architecture

56
7 Ultrasparc External Interfaces

88
- Introduction
  88
- Overview of Ultrasparc External Interfaces
  88
- Interaction between E-Cache and UDB
  91
- SYSADDR Bus Arbitration Protocol
  99
- Ultrasparc Interconnect Transaction Overview
  107
- Cache Coherence Protocol
  109
- Cache Coherent Transactions
  117
- Non-Cached Data Transactions
  124
- S_Rto/S_Err
  126
- S_Req
  126
- Writeback Issues
  127
- Interrupts (P_INT_REQ)
  131
- P_REPLY and S_REPLY
  132
- Multiple Outstanding Transactions
  141
- Transaction Set Summary
  144
- Transaction Sequences
  146
- Interconnect Packet Formats
  153
- Writeinvalidate
  158
8 Address Spaces, Asis, Asrs, and Traps

160
- Overview
  160
- Physical Address Space
  160
- Ancillary State Registers
  171
- Other Ultrasparc Registers
  173
- Supported Traps
  173
9 Interrupt Handling

176
- Interrupt Vectors
  176
- Interrupt Global Registers
  178
- Interrupt ASI Registers
  178
- Software Interrupt (SOFTINT) Register
  181
10 Reset and Red_State

184
- Overview
  184
- Red_State Trap Vector
  186
- Machine State after Reset and in Red_State
  186
11 Error Handling

190
- Overview
  190
- Memory Errors
  193
- Memory Error Registers
  194
- Ultrasparc Data Buffer (UDB) Control Register
  200
- Overwrite Policy
  200
  - Section III - Ultrasparc and SPARC-V9
    202
12 Instruction Set Summary

204
13 Ultrasparc Extended Instructions

210
- Introduction
  210
- Shutdown
  210
- Graphics Data Formats
  211
- Graphics Status Register (GSR)
  212
- Graphics Instructions
  213
- Memory Access Instructions
  240
14 Implementation Dependencies

250
- SPARC-V9 General Information
  250
- SPARC-V9 Integer Operations
  255
- SPARC-V9 Floating-Point Operations
  257
- SPARC-V9 Memory-Related Operations
  262
- Non-SPARC-V9 Extensions
  264
15 SPARC-V9 Memory Models

270
16 Code Generation Guidelines

276
- Hardware / Software Synergy
  276
- Instruction Stream Issues
  276
- Data Stream Issues
  287
17 Grouping Rules and Stalls

296
- Introduction
  296
- General Grouping Rules
  297
- Instruction Availability
  298
- Single Group Instructions
  298
- Integer Execution Unit (IEU) Instructions
  299
- Control Transfer Instructions
  302
- Load / Store Instructions
  305
- Floating-Point and Graphic Instructions
  310
- Appendixes
  
  316
Debug and Diagnostics Support

318
- Overview
  318
- Diagnostics Control and Accesses
  318
- Dispatch Control Register
  318
- Floating-Point Control
  319
- Watchpoint Support
  319
- Lsu_Control_Register
  321
- I-Cache Diagnostic Accesses
  324
- D-Cache Diagnostic Accesses
  329
- E-Cache Diagnostics Accesses
  330
Performance Instrumentation

334
- Overview
  334
- Performance Control and Counters
  334
- PCR/PIC Accesses
  336
- Performance Instrumentation Counter Events
  336
Power Management

342
- Power-Up
  343
- C.3 Power-Up
  343
- Introduction
  344
- Interface
  344
- D.1 Introduction
  344
- Test Access Port (TAP) Controller
  345
D. IEEE 1149.1 Scan Interface

346
- Instruction Register
  348
- Instructions
  348
- D.4 Instruction Register
  348
- Public Test Data Registers
  350
- Introduction
  352
- Pin Descriptions
  352
- E.1 Introduction
  352
E. Pin and Signal Descriptions

354
- Signal Descriptions
  356
- E.3 Signal Descriptions
  356
ASI Names

360
- Introduction
  360
  - F.1 Introduction
    360
  - F. ASI Names
    362
- Introduction
  366
- Summary
  366
- G.1 Introduction
  366
- References to Model-Specific Information
  367
G. Differences between Ultrasparc Models

368
- Back Matter
  370
- Glossary
  
  372
- Bibliography
  
  378
  - General References
    378
  - Sun Microelectronics (SME) Publications
    379
  - How to Contact SME
    380
  - On Line Resources
    380

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Sun Microsystems UltraSPARC-I Manuals

Sun Microsystems UltraSPARC-I User Manual (410 pages)

Table of Contents

1 Ultrasparc Basics

Preface

2 Processor Pipeline

3 Cache Organization

4 Overview of the MMU

5 Cache and Memory Interactions ........................................................................................ Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | Www.artisantg.com

6 MMU Internal Architecture

7 Ultrasparc External Interfaces

8 Address Spaces, Asis, Asrs, and Traps

9 Interrupt Handling

10 Reset and Red_State

11 Error Handling

12 Instruction Set Summary

13 Ultrasparc Extended Instructions

14 Implementation Dependencies

15 SPARC-V9 Memory Models

Section IV - Producing Optimized Code

16 Code Generation Guidelines

17 Grouping Rules and Stalls

Appendixes

Debug and Diagnostics Support

Performance Instrumentation

Power Management

D. IEEE 1149.1 Scan Interface

E. Pin and Signal Descriptions

ASI Names

G. Differences between Ultrasparc Models

Glossary

Bibliography

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