Sun Microsystems UltraSPARC-I User Manual page 401

raSPARC User's Manual
el distance 7
el orderings 197
L_BYPASSS signal 343
LBYPASS signal 342
, see Physical Address Data Watchpoint Mask
(PM) field of LSU_Control_Register
ERGE instruction 206
nt-to-point write-invalidate protocol 94
ulation count (POPC) instruction 240
t_ID field 141
t_ID signal 85 to 86
t_id signal 86
wer on
clearing AFSR to avoid false errors 176
trap 158
er_on_reset
wer-down mode 196, 253, 327
restart 328
wer-On Reset (POR) 145, 170
wer-on Reset (POR) 175
wer-On Reset (POR) pin 328
wer-On-Reset (POR) 239
wer-on-Reset (POR) 119
see Physical Address Data Watchpoint Read
Enable (PR) field of LSU_Control_Register
cise exception model 7
cise traps 40, 236
fech and Dispatch Unit (PDU) 14
fetch and Dispatch Unit (PDU) 6, 13
illustrated 5
fetch unit 4
EFETCHA instruction 248
fetchable 359
EQ_DQ, see Number of Entries in P_REQ Data
Read Queue (PREQ_DQ) field of UPA_
CONFIG register
EQ_DQ, see Number of Entries in P_REQ Data
Read Queue (PREQ_DQ) field of UPA_
PORT_ID register
EQ_DQ, see Number of Entries in P_REQ Data
Write Queue (PREQ_DQ) field of UPA_
CONFIG register
EQ_DQ, see Number of Entries in P_REQ Data
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
Write Queue (PREQ_DQ) field of UPA_
Primary Context Register 57
PRIV, see Privileged (PRIV) field of PCR register
Privilege (PRIV) field of AFSR 177
privilege (PRIV) field of PSTATE register 180
privilege violation 60
privileged 47, 360
Privileged (P) field of TTE 44
Privileged (PR) field of SFSR register 59
Privileged (PRIV) field of PCR register 157, 319
to 320
Privileged (PRIV) field of PSTATE register 34, 44,
48 to 49, 256, 359 to 360, 362
Privileged Access (PRIV) field of AFSR 181
privileged mode 360
trap 34, 47, 49, 51, 156 to 157, 159,
privileged_action
164 to 166, 239, 256, 319
trap 157, 159, 166 to 167, 196,
privileged_opcode
249, 304, 319
privilege-error field (PRIV) of AFSR 180
Processor Capabilities (PCAP) field of UPA_
CONFIG register 156
Processor Configuration (PCON) field of UPA_
CONFIG register 155
processor front end components 261
processor interrupt level (PIL) 167
Processor Interrupt Level (PIL) field of PSTATE
register 250
processor interrupt level (PIL) field of PSTATE
register 167
processor memory model 233
processor-to-UPA frequency ratio 292
program counter 360
program order 32
protection violation 49
protocol
cache coherence 94
PSO 295
mode 30, 32
PSO memory model 249
PSTATE 232
PSTATE global register selection encodings 252
PSTATE Register 251, 253, 285
PW, see Physical Address Data Watchpoint Write
P