Sun Microsystems UltraSPARC-I User Manual page 303

UltraSPARC User's Manual
If the delay slot of a DCTI is aligned on a 32-byte address boundary (that is, the
DCTI is the last instruction in a cache line and the delay slot contains the first in-
struction in the next cache line), then the DCTI cannot be grouped with instruc-
tions from the predicted stream. For example:
setcc
BPcc
FADD (32-byte aligned)
FMUL (branch target)
If the second instruction of the predicted stream is aligned on a 32-byte address
boundary, then the DCTI cannot be grouped with that instruction. For example:
BPcc
ADD (delay slot)
FADD
FMUL (32-byte aligned)
The delay slot of a DCTI cannot be grouped with instructions from the predicted
stream of another DCTI following the delay slot. For example:
FADD (delay slot 1)
BPcc
ADD (delay slot 2)
FMUL (branch target)
When a control transfer is mispredicted, the instruction buffer and instructions
younger than the delay slot in the pipe are flushed, effectively inserting four bub-
bles in the pipe. An
instructions in the correct branch stream to stall until the
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G E C N
1
G E C N
1
G E C N
1
G E C
G E C N
1
G E C N
1
G E C N
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G E C
G E C N
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G E C
or in the mispredicted stream cause dependent
FDIV FSQRT
N N W
2 3
N N W
2 3
N N W
2 3
N N N W
1 2 3
N N W
2 3
N N W
2 3
N N W
2 3
N N N W
1 2 3
N N W
2 3
N N W
2 3
N N W
2 3
N N N W
1 2 3
or
FDIV FSQRT
reaches