Sun Microsystems UltraSPARC-I User Manual page 43

raSPARC User's Manual
Cache flushing is required in the following cases:
I-Cache:
Flush is needed before executing code that is modified by a local store instruction
other than block commit store, see Section 3.1.1.1, "Instruction Cache (I-Cache)."
This is done with the FLUSH instruction or using ASI accesses. See Section A.7,
"I-Cache Diagnostic Accesses," on page 309. When ASI accesses are used, soft-
ware must ensure that the flush is done on the same processor as the stores that
modified the code space.
D-Cache:
Flush is needed when a physical page is changed from (virtually) cacheable to
(virtually) noncacheable, or when an illegal address alias is created (see Section
5.2.1, "Address Aliasing Flushing," on page 28). This is done with a displacement
flush (see Section 5.2.3, "Displacement Flushing," on page 29) or using ASI
accesses. See Section A.8, "D-Cache Diagnostic Accesses," on page 314.
E-Cache:
Flush is needed for stable storage. Examples of stable storage include battery-
backed memory and transaction logs. This is done with either a displacement
flush (see Section 5.2.3, "Displacement Flushing," on page 29) or a store with
ASI_BLK_COMMIT_{PRIMARY,SECONDARY}. Flushing the E-Cache will flush
the corresponding blocks from the I- and D-Caches, because UltraSPARC main-
tains inclusion between the external and internal caches. See Section 5.2.2, "Com-
mitting Block Store Flushing," on page 29.
2.1 Address Aliasing Flushing
A side-effect inherent in a virtual-indexed cache is illegal address aliasing. Aliasing
occurs when multiple virtual addresses map to the same physical address. Since
UltraSPARC's D-Cache is indexed with the virtual address bits and is larger than
the minimum page size, it is possible for the different aliased virtual addresses to
end up in different cache blocks. Such aliases are illegal because updates to one
cache block will not be reflected in aliased cache blocks.
Normally, software avoids illegal aliasing by forcing aliases to have the same ad-
dress bits (virtual color) up to an alias boundary. For UltraSPARC, the minimum
alias boundary is 16Kb; this size may increase in future designs. When the alias
boundary is violated, software must flush the D-Cache if the page was virtual
cacheable. In this case, only one mapping of the physical page can be allowed in
the D-MMU at a time. Alternatively, software can turn off virtual caching of ille-
gally aliased pages. This allows multiple mappings of the alias to be in the
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D-MMU and avoids flushing the D-Cache each time a different mapping is refer-