Sun Microsystems UltraSPARC-I User Manual page 253

raSPARC User's Manual
and FFFF F7FF FFFF FFFF
Address translation and MMU related descriptions can be found in Section 4.2,
"Virtual Address Translation," on page 21.
Out of Range VA
(VA "Hole")
Figure 14-2 UltraSPARC's 44-bit Virtual Address Space, with Hole (Same as Figure 4-2)
Note: Throughout this document, when virtual address fields are specified as
64-bit quantities, they are assumed to be sign-extended based on VA<43>.
A number of state registers are affected by the reduced virtual address space.
TBA, TPC, TNPC, VA and PA watchpoint, and DMMU SFAR registers are 44-bits,
sign-extended to 64-bits on read accesses. No checks are done when these regis-
ters are written by software. It is the responsibility of privileged software to prop-
erly update these registers.
An out of range address during an instruction access causes an
instruction_access_exception
If the target address of a JMPL or RETURN instruction is an out-of-range address
and PSTATE.AM is not set, a trap is generated with the PC = the address of the
JMPL or RETURN instruction and the trap type in the I-MMU SFSR register. This
instruction_access_exception
RETURN (
illegal_instruction
TURN,
mem_address_not_aligned
to the target. The trap handler can determine the out-of-range address by decod-
ing the JMPL instruction from the code.
All other control transfer instructions trap on the PC of the target instruction
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along with different status in the I-MMU SFSR register. Because the PC is sign-ex-
inclusive are termed "out-of-range" and are illegal.
16
trap if PSTATE.AM is not set.
trap is lower priority than other traps on the JMPL or
due to nonzero reserved fields in the JMPL or RE-
trap, or
window_fill
FFFF FFFF FFFF FFFF
FFFF F800 0000 0000
FFFF F7FF FFFF FFFF
0000 0800 0000 0000
0000 07FF FFFF FFFF
0000 0000 0000 0000
trap), because it really applies