Sun Microsystems UltraSPARC-I User Manual page 101

raSPARC User's Manual
Addr_Valid is driven following the same rules as SYSADDR signals.
Addr_Valid must be deasserted in the last cycle it is driven. The SC must
contain a holding amplifier to maintain the previously asserted state of
each Addr_Valid signal when it is undriven.
4.3.1 Arbitration Rules
The interface that is currently driving (or allowed to drive) SYSADDR and
Addr_Valid is called the C
lowed to drive) SYSADDR and Addr_Valid during the previous cycle is called
the L P
AST ORT
D , but it is never the L
RIVER
after its transaction has completed, the value of L
the interface that last drove the bus before the SC.
The arbitration protocol has the following rules:
1. After reset, the UltraSPARC with port_ID<1:0>=0 is the initial L
D .
RIVER
2. None of the interconnect masters or the SC may assert their requests until
44 processor cycles following the de-assertion of RESET_L.
3. The UltraSPARC for which L
advantage of a rule that allows request, then drive. Otherwise, the
UltraSPARC will minimally see a request, wait, then drive latency. The SC
will always see this minimal latency, since it is not included as a potential
L P
AST ORT
4. If no requests were asserted during the last cycle, the next cycle's value for
L P
AST ORT
5. If an UltraSPARC sees that L
may assert its request in next cycle and drive a packet in the cycle after
that. This reduced-latency-to-drive condition is disabled if any other
requests are asserted during the cycle before request assertion.
Since the arbiter logic can use only registered requests, the reduced-
latency-to-drive condition actually would be disabled during the next
cycle, and the port would rely on the normal arbitration logic of rule 9,
which adds one more cycle of latency.
6. The C
URRENT
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request for one cycle in the presence of another SC or interconnect request.
D
URRENT
D . Note that the System Controller can become the C
RIVER
P
AST ORT
AST
D .
RIVER
D remains the same as this cycle's value.
RIVER
AST
D relinquishes ownership of the bus by deasserting its
RIVER
. The interface that drove (or was al-
RIVER
D . When SC relinquishes the control
RIVER
P
AST ORT
P D =port_ID<1:0> can take
ORT RIVER
P D equals its port_id<1:0>, it
ORT RIVER
URRENT
D is the value of
RIVER
P
AST ORT