Sun Microsystems UltraSPARC-I User Manual page 407

raSPARC User's Manual
hit 14
instruction 17
miss 14
miss handler 29
miss strategy 8
reset 55
nslation Lookaside Buffer (TLB) miss
handler 229
nslation Storage Buffer (TSB) 23, 42, 44, 61,
229, 247, 267
nslation Table Entry (TTE) 41, 48
illustrated 41
p 361
resolution 15
p Base Address (TBA) register 361
p Enable Mask (TEM) field of FSR
register 242 to 243, 245 to 247
p global registers 251
p registers 7
p stack 236, 252
p state registers 236
trap 159
_instruction
ps
MMU generated 47
tate output enables
registered 85
ST_L IEEE 1149.1 signal 330
ST_L pin 338, 341
ST_L signal 342 to 343
locked items 47
caching 45
miss handler 46
organization 45
pointer logic 70
Pointer Register 63
Register 44
Tag Target Register 47, 57
_Base 61
_Base field of TSB Register 61
_Base, see Base Address (TSB_Base) field of TSB
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register
TSB_Size, see TSB Size (TSB_Size) field of TSB
register
TSO 295
mode 30, 32
ordering 30
TSO memory model 249
TSTATE 253
TSYN_WR_L pin 340
TSYN_WR_L signal 341
turn-around penalty 9
none for write-to-read transition 83
read-to-write transition 83
TWE_L signal 79
two-dimensional image processing 7
U
UART 30
UDB Error Enable Register 184
UDB_CE pin 338
UDB_CE signal 343
UDB_CEH pin 337
UDB_CEH signal 342
UDB_CEL pin 337
UDB_CEL signal 342
UDB_CNTL pins 337 to 338
UDB_CNTL signals 342 to 343
UDB_H pin 338
UDB_H signal 343
UDB_UE pin 338
UDB_UE signal 343
UDB_UEH pin 337
UDB_UEH signal 342
UDB_UEL pin 337
UDB_UEL signal 342
UltraSPARC extentions to SPARC-V9 10
UltraSPARC_I Data Buffer (UDB) Error
Register 175
UltraSPARC-I architecture
overview 3
UltraSPARC-I block diagram 5
UltraSPARC-I Data Buffer (UDB) 10, 74, 127, 175,
184, 196, 291, 294
U