Sun Microsystems UltraSPARC-I User Manual page 357

UltraSPARC User's Manual
Table E-8 UltraSPARC Signals (Continued)
Function
System Interface Controls
System Reply
Processor Reply
Address Bus Arbitration
Address Bus Request
Address Packet Valid
SC Request for interconnect addr bus
SC Data Stall
UDB Interface
Uncorrectable Error (High)
Uncorrectable Error (Low)
Correctable Error (High)
Correctable Error (Low)
UDB Control
Clock Interface
Differential Clock Input A
Differential Clock Input B
PLL loop filter connection
Low Frequency/D.C. signal
UDB Clock A (copy)
UDB Clock B (copy)
Phase Lock Loop Bypass
Level 5 Clock
IEEE 1149.1 (JTAG) Interface/Debug
IEEE 1149.1 Test Data Out
IEEE 1149.1 Test Data Input
IEEE 1149.1 Test Clock Input
IEEE 1149.1 Test Mode Select
IEEE 1149.1 Test Reset Input
SRAMs Test Mode
Test/Debug/Instrument Bus
Clock Stopper (debug)
Initialization
Reset
XIR Reset (NMI)
Power Down Mode
1.
ECAD<19:0> for UltraSPARC-II
2.
ECAT<17:0> for UltraSPARC-II
3.
LOOP_CAP present in UltraSPARC-I only
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Name Count
S_REPLY<3:0> 4
P_REPLY<4:0> 5
NODE_RQ<2:0> 3
NODEX_RQ 1
ADR_VLD 1
SC_RQ 1
DATA_STALL 1
UDB_UEH 1
UDB_UEL 1
UDB_CEH 1
UDB_CEL 1
UDB_CNTL<4:0> 5
CLKA 1
CLKB 1
3
LOOP_CAP 1
DC_SPARE 1
SDBCLKA 1
SDBCLKB 1
PLLBYPASS 1
L5CLK 1
TDO 1
TDI 1
TCK 1
TMS 1
TRST_L 1
RAM_TEST 1
MISC_BIDIR<14:0> 15
EXT_EVENT 1
RESET_L 1
XIR_L 1
EPD 1
I/O
I
O
I
O
I/O
I
I
I
I
I
I
O
I
I
I
I
I
I
I
O
O
I
I
I
I
I
I/O
I/O
I
I
I