Sun Microsystems UltraSPARC-I User Manual page 312

MOVcc based on a floating-point condition code can be in the same group as an
FCMP{E}{s,d}, however, if they reference different condition codes. For example:
FCMP fcc0, f2, f4
MOVcc fcc1, f6, f8
Latencies between dependent floating-point and graphics instructions are shown
in Table 17-1, "Latencies for Floating-Point and Graphics Instructions," on
page 300. Latencies depend on the instruction generating the result (use the left
column of the table to select a row) and the operation using the result (use the
top row of the table to select a column). For example:
FADDs f2, f3, f0
FMULs f6, f1, f2
FADDs f2, f3, f0
FMOVs f6,f1,f2
,
FDIV{s,d} FSQRT{s,d}
wait in the G Stage for the remaining latency of the previous divide or square
root, even if there is no data dependency. An FGA or FGM instruction (see
Table 17-1) that first enters the G Stage one cycle before an
dent instruction would be released will be held for one clock, regardless of data
dependency.
and
FDIV FSQRT
M-Class operation cannot be dispatched in the third clock before the divide is fin-
ished. A load use stall that occurs in the third or fourth clock before normal di-
vide completion will delay completion by a corresponding amount.
and
FDIV FSQRT
point loads) for the same time as a source register dependency.
Graphics instructions,
precision register containing the single-precision result for data dependency
checking. For example:
FORs f2, f4, f0
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G E C
G E C
G E C
G E C
, block load, block store,
use the floating-point multiplier for final rounding, so an
stall earlier instructions with the same rd (including floating-
, ,
FdTOi FxTOs FdTOs
G E C
17. Grouping Rules and Stalls
N N N W
1 2 3
N N N W
1 2 3
N N N W
1 2 3
G E C N N
1
N N N W
1 2 3
G E C N
and
ST{X}FSR, LD{X}FSR
FDIV
, and
FDIVs, FSQRTs
N N N W
1 2 3
N
2 3
N
1 2
instructions
or depen-
FSQRT
lock the double-