Mmu Internal Architecture; Introduction; Translation Table Entry (Tte) - Sun Microsystems UltraSPARC-I User Manual

MMU Internal Architecture

6.1 Introduction

This chapter provides detailed information about the UltraSPARC Memory Man-
agement Unit. It describes the internal architecture of the MMU and how to pro-
gram it.

6.2 Translation Table Entry (TTE)

The Translation Table Entry, illustrated in Figure 6-1, is the UltraSPARC equiva-
lent of a SPARC-V8 page table entry; it holds information for a single page map-
ping. The TTE is broken into two 64-bit words, representing the tag and data of
the translation. Just as in a hardware cache, the tag is used to determine whether
there is a hit in the TSB. If there is a hit, the data is fetched by software.
G —
63 62
V Size
63 62 61 60
Figure 6-1
G: Global. If the Global bit is set, the Context field of the TTE is ignored
during hit detection. This allows any page to be shared among all (user
or supervisor) contexts running in the same processor. The Global bit is
duplicated in the TTE tag and data to optimize the software miss handler.
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Context —
61 60 48 47 42
NFO IE Soft2 Diag PA<40:13>
59 58 50 49 41 40
Translation Table Entry (TTE) (from TSB)
VA_tag<63:22>
41
Soft L CP CV E
13 12 7 6 5 4 3
6
Tag
0
P W G
Data
2 1 0