Sun Microsystems UltraSPARC-I User Manual page 395

raSPARC User's Manual
replaces SPARC-V8 LD 273
subroutine 272
el-1 cache 17
flushing 27
el-1 instruction cache 309
el-2 cache 18, 27
e-endian 219
e-endian ASIs 228
e-endian byte order 145, 226
lock condition
avoiding 93
d
outstanding 294
d / Store Unit (LSU) 8
address generation adder 6
illustrated 5
d Buffer 8, 14 to 15
illustrated 5
d buffer 4, 32, 39, 275 to 278, 290, 292, 294, 323
to 324
depth 275
required depth 276
d buffer timing 275
d data
returned in order 292
d Data Parity Error (LDP) field of AFSR 181
d hit bypassing load miss
not support on UltraSPARC-I 277
d latencies 277
d Store Unit (LSU) 49
d use
stall counts 322
d use stall 297
ds
always execute in order 276
ds to the same D-Cache sub-block 277
d-use dependency 269
k (L) field of TTE 43
p unrolling 272
OP_CAP pin 340
pback (not allowed) 116
OPCAP signal 342
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U_Control_Register 17 to 19, 54, 169, 177, 305
illustrated 306
M
M Class instructions 296
machine state after reset 171
machine state in RED_state 171
mandatory SPARC-V9 ASRs 156
manuf field of VER register 241
manuf, see Manufacturer (manuf) field of VER
register
mask field of VER register 241
mask, see Mask Identifier (mask) field of VER
register
master
UltraSPARC-I as 74
Master Interface (valid S_REPLY types) 130
master UltraSPARC-I 84
MAXTL 171, 236
maxtl field of VER register 242
maxtl, see Maximum Trap Level (maxtl) field of VER
register
maxwin field of VER register 242
maxwin, see Maximum CWP (maxwin) field of VER
register
may 359
MCAP pin 340
mem_address_not_aligned
159, 226, 228 to 229, 231, 238, 273, 303
MEMBAR
#LoadLoad
MEMBAR #LoadStore
295
MEMBAR
#Lookaside
MEMBAR #Lookaside
30
#StoreLoad
MEMBAR #MemIssue
to 295
MEMBAR #StoreLoad
233, 257, 293 to 294
MEMBAR
#StoreStore
295
and STBAR 33
MEMBAR 29, 32 to 33, 39, 56, 58, 67, 146,
#Sync
M
trap 47, 49, 56, 58, 154,
32, 256 to 257
32, 232 to 233, 294 to
30, 33, 256 to 258
vs MEMBAR
32 to 33, 257 to 258, 293
30, 32, 40, 112, 232 to
33, 233, 248, 294 to