Code Generation Guidelines; Hardware / Software Synergy; Instruction Stream Issues - Sun Microsystems UltraSPARC-I User Manual

Code Generation Guidelines

16.1 Hardware / Software Synergy

One of the goals set for UltraSPARC was for the processor to execute SPARC-V8
binaries efficiently, providing around three times the performance of existing ma-
chines running the same code. A significantly larger performance gain can be ob-
tained if the code is re-compiled using a compiler specifically designed for
UltraSPARC. Several features are provided on UltraSPARC that can only be taken
advantage of by using modern compiler technology. This technology was not
available previously, mainly because the hardware support was not sufficient to
justify its development.

16.2 Instruction Stream Issues

16.2.1 UltraSPARC Front End
The front end of the processor consists of the Prefetch Unit, the I-Cache, the next
field RAM, the branch and set prediction logic, and the return address stack. The
role of the front end is to supply as many valid instructions as possible to the
grouping logic and eventually to the functional units (the ALUs, floating-point
adder, branch unit, load/store pipe, etc.).
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