Sun Microsystems UltraSPARC-I User Manual page 266

14.5.6 Partial Stores
UltraSPARC supports 8-/16-/32-bit partial stores to memory. See Section 13.6.1,
"Partial Store Instructions," on page 225.
14.5.7 Short Floating-Point Loads and Stores
UltraSPARC supports 8-/16-bit loads and stores to the floating-point registers.
See Section 13.6.2, "Short Floating-Point Load and Store Instructions," on page
227.
14.5.8 Atomic Quad-load
UltraSPARC supports 128-bit atomic load operations to a pair of integer registers.
See Section 13.6.3, "Atomic Quad Load," on page 229.
14.5.9 PSTATE Extensions: Trap Globals
UltraSPARC supports two additional sets of eight 64-bit global registers: inter-
rupt globals and MMU globals. These additional registers are called the "trap
globals." Two 1-bit fields, PSTATE.IG and PSTATE.MG, have been added to the
PSTATE register to select which set of global registers to use. The PSTATE.IG and
PSTATE.MG bits are also stored with the rest of the PSTATE register in the
TSTATE register when a trap is taken. See Chapter 9, "Interrupt Handling" for a
description of the trap global registers. See Table 10-1, "Machine State After Reset
and in RED_state," on page 172 for the states of these bits on reset.
Table 14-12
Bits
<11>
<10>
<9>
<8>
<7:6>
<5>
<4>
<3>
<2>
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<1>
Extended PSTATE Register
Field Use
IG Interrupt globals enable
MG MMU globals enable
CLE Current little endian enable
TLE Trap little endian enable
MM Memory Model
RED RED_state enable
PEF Floating point enable
AM 32-bit address mask enable
PRIV Privileged mode
IE Interrupt enable
14. Implementation Dependencies
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