Overview Of The Mmu; Introduction; Virtual Address Translation - Sun Microsystems UltraSPARC-I User Manual

Overview of the MMU

4.1 Introduction

This chapter describes the UltraSPARC Memory Management Unit as it is seen by
the operating system software. The UltraSPARC MMU conforms to the require-
ments set forth in The SPARC Architecture Manual, Version 9.
Note: The UltraSPARC MMU does not conform to the SPARC-V8 Reference
MMU Specification. In particular, the UltraSPARC MMU supports a 44-bit virtual
address space, software TLB miss processing only (no hardware page table walk),
simplified protection encoding, and multiple page sizes. All of these differ from
features required of SPARC-V8 Reference MMUs.

4.2 Virtual Address Translation

The UltraSPARC MMU supports four page sizes: 8 Kb, 64 Kb, 512 Kb, and 4 Mb.
It supports a 44-bit virtual address space, with 41 bits of physical address. During
each processor cycle the UltraSPARC MMU provides one instruction and one
data virtual-to-physical address translation. In each translation, the virtual page
number is replaced by a physical page number, which is concatenated with the
page offset to form the full physical address, as illustrated in Figure 4-1 on page
22. (This figure shows the full 64-bit virtual address, even though UltraSPARC
supports only 44 bits of VA.)
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