Sun Microsystems UltraSPARC-I User Manual page 93

raSPARC User's Manual
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Store buffer requests. The store buffer priority is made higher than the load
buffer priority when the store buffer reaches five entries; it remains higher
until the number of entries drops to two.
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The request for the first 16 bytes of data from the I-Cache/Prefetch Unit. After
the first clock of an I-Cache request, its priority becomes higher than load and
store buffer requests.
The UDB contains:
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A read buffer that holds a model-dependent number of 64-byte lines coming
from main memory; these satisfy E-Cache read misses or noncacheable reads.
Table 7-3 shows the supported buffer depth for each UltraSPARC model.
Table 7-4 Supported Read Buffer Depth
# of Entries
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A model-dependent number of 64-byte buffers to hold writebacks, block
stores, and outgoing interrupt vectors. The writeback buffer(s) are in the
coherence domain; consequently, it can be used to satisfy copyback requests
from the system. Table 7-5 shows the number of Writeback buffer entries for
each UltraSPARC model. Note: Models that support more than one Writeback
buffer entry can be restricted to using only one entry.
Table 7-5 Supported Number of Writeback Buffer Entries
# of Entries
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Eight 16-byte noncacheable store buffers.
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A 24-byte buffer to hold an incoming Interrupt Vector. (Each UDB chip
contains a 24-byte interrupt vector buffer, but only one buffer is used.)
3.2 UltraSPARC E-Cache and UDB Transactions
This section describes transactions occurring between UltraSPARC, the E-Cache,
and the UDB. Interconnect transactions are described in a later section. Transi-
tions in the timing diagrams show what is seen at the pins of UltraSPARC.
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Cache line states are defined in Section 7.6, "Cache Coherence Protocol," on page
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