raSPARC User's Manual
Table 12-1
Complete UltraSPARC Instruction Set (Continued)
Opcode
BC (SUBCcc)
Subtract with carry (and modify condition codes)
AP
Swap integer register with memory
APA
Swap integer register with memory in alternate space
DDcc
Tagged add and modify condition codes (trap on overflow)
ADDccTV)
UBcc
Tagged subtract and modify condition codes (trap on overflow)
UBccTV)
Trap on integer condition codes
IV (UDIVcc)
Unsigned integer divide (and modify condition codes)
IVX
64-bit unsigned integer divide
MUL (UMULcc)
Unsigned integer multiply (and modify condition codes)
RASI
Write ASI register
RASR
Write ancillary state register
RCCR
Write condition codes register
RFPRS
Write floating-point registers state register
RPR
Write privileged register
RY
Write Y register
OR (XNORcc)
Exclusive-nor (and modify condition codes)
R (XORcc)
Exclusive-or (and modify condition codes)
traSPARC-I does not implement the PREFETCH and PREFETCHA instructions.
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Description
Ext
Ref
A.55
A.56
A.57
A.58
A.59
A.60
A.10
A.36
A.37
A.62
A.62
A.62
A.62
A.61
A.62
A.31
A.31
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